Boundary Scan in Low-Power Flash Devices
18- 2
v1.1
Actel’s Flash Families Support the JTAG Feature
The low-power flash families listed in
Table 18-1 support the JTAG feature and the functions
described in this document.
Actel's low-power flash devices (listed in
Table 18-1) provide a selection of low-power, secure, live-at-
power-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and
incorporate FlashLock technology, which provides a unique combination of reprogrammability and
design security without external overhead. Only low-power flash FPGAs can offer these advantages.
Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic
devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD
alternatives, while ProASIC3L devices offer a balance of low power and higher performance.
Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to
and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM
and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode.
Flash*Freeze technology simplifies power management through I/O and clock management
without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting
Flash*Freeze mode takes less than 1 s.
The Actel Fusion family, based on the highly successful ProASIC3 flash FPGA architecture, has been
designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many
peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive
outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory,
including the flash array blocks, is greater than that found in SRAM FPGAs.
IGLOO Terminology
In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in
Table 18-1. Where the information applies to only one family or limited devices, these exclusions
will be explicitly stated.
ProASIC3 Terminology
In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as
listed in
Table 18-1. Where the information applies to only one family or limited devices, these
exclusions will be explicitly stated.
Table 18-1 Low-Power Flash Families
Family1
Description
Timing Numbers2
Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze
technology
Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze
technology and enhanced I/O capabilities
IGLOO devices enhanced with higher density, five additional
PLLs, and additional I/O standards
Low-power high-performance 1.2 V FPGAs with Flash*Freeze
technology
Low-power, high-performance 1.5 V FPGAs
ProASIC3 enhanced with higher density, five additional PLLs, and
additional I/O standards
Low-power, high-performance FPGAs qualified for automotive
applications
Low-power mixed-signal Programmable System Chip (PSC)
Notes:
1. The family names are linked to the appropriate product brief.
2. The timing number links go to the relevant timing numbers in the datasheet.