參數(shù)資料
型號: A3251LUATL
廠商: Allegro MicroSystems, Inc.
英文描述: Field-Programmable, Chopper-Stabilized Unipolar Hall-Effect Switches
中文描述: 現(xiàn)場可編程斬波穩(wěn)定單極霍爾效應(yīng)開關(guān)
文件頁數(shù): 11/15頁
文件大?。?/td> 418K
代理商: A3251LUATL
11
A3250-DS
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
A3250 and A3251
V
PH
V+
t
V
PM
V
PL
0
Address 1
Address 2
Address
n
(
63)
Figure 5. Pulse sequence to select addresses
Falling edge of final B
OP
address digit
V
PH
V+
t
V
PM
V
PL
0
Encode Lock Bit
Enable
Address
Blow
7 pulses
65 pulses
Figure 6. Pulse sequence to encode lock bit
Lock Bit Programming
.
After the desired B
OP
calibration value
is programmed, and all of the corresponding bitfield-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (bitfield address 65) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bitfields, as shown in figure 6.
Address Selection
.
After addressing mode is enabled, the
target bitfield address, is indicated by a series of VPM pulses,
as shown in figure 3. When provisionally trying a value, this
sequence is followed by a short V
PH
pulse, which serves to
delimit the address and set the corresponding bitfield. When
permanently setting a bitfield, the V
PH
pulse is continued for a
longer period of time, suffienct to not only set the bitfield to 1,
but also to blow the bitfield fuse.
Enabling Addressing Mode
.
The first segment of code is a
keying sequence used to enable the bitfield addressing mode. As
shown in figure 4, this segment consists of one short V
PH
pulse,
seven or more V
PM
pulses, and one V
PH
pulse, with no supply
interruptions. This sequence is designed to prevent the device
from being programmed accidentally, such as by noise on the
supply line.
V
PH
V+
t
V
PM
V
PL
0
Minimum 7 pulses
Figure 4. Addressing mode enable pulse sequence
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