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參數(shù)資料
| 型號： | A3230LUA-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 512K |
| 描述： | IC SW HALL EFFECT CHOPPER 3-SIP |
| 產(chǎn)品培訓(xùn)模塊： | Current Sensor |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 傳感范圍： | 25G 跳閘，-25G 釋放 |
| 類型： | 雙極卡鎖 |
| 電源電壓： | 3.6 V ~ 24 V |
| 電流 - 電源： | 3.5mA |
| 電流 - 輸出（最大）： | 60mA |
| 輸出類型： | 數(shù)字式，開漏極 |
| 特點： | 穩(wěn)壓電壓 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 3-SIP |
| 供應(yīng)商設(shè)備封裝： | 3-SIP |
| 包裝： | 散裝 |
| 產(chǎn)品目錄頁面： | 1139 (CN2011-ZH PDF) |
| 其它名稱： | 620-1045 |
Chopper-Stabilized Hall Effect Bipolar Switch
A3230
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 2. Chopper Stabilization Circuit (Dynamic Quadrature Offset Cancellation)
Amp
Regulator
Clock/Logic
Hall Element
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall element. This makes it dif cult to process the signal while
maintaining an accurate, reliable output over the speci ed oper-
ating temperature and voltage ranges.
Chopper stabilization is a unique approach used to minimize
Hall offset on the chip. The patented Allegro technique, namely
Dynamic Quadrature Offset Cancellation, removes key sources
of the output drift induced by thermal and mechanical stresses.
This offset reduction technique is based on a signal modulation-
demodulation process. The undesired offset signal is separated
from the magnetic- eld-induced signal in the frequency domain,
through modulation. The subsequent demodulation acts as a
modulation process for the offset, causing the magnetic- eld-
induced signal to recover its original spectrum at baseband,
while the dc offset becomes a high-frequency signal. The
magnetic- eld-induced signal then can pass through a low-pass
lter, while the modulated dc offset is suppressed. This con gu-
ration is illustrated in gure 2.
The chopper stabilization technique uses a 200 kHz high-fre-
quency clock. For demodulation process, a sample and hold
technique is used, where the sampling is performed at twice the
chopper frequency (400 kHz). This high-frequency operation
allows a greater sampling rate, which results in higher accuracy
and faster signal-processing capability. This approach desensi-
tizes the chip to the effects of thermal and mechanical stresses,
and produces devices that have extremely stable quiescent Hall
output voltages and precise recoverability after temperature
cycling. This technique is made possible through the use of a
BiCMOS process, which allows the use of low-offset, low-noise
ampli ers in combination with high-density logic integration and
sample-and-hold circuits.
The repeatability of magnetic- eld-induced switching is affected
slightly by a chopper technique. However, the Allegro high-
frequency chopping approach minimizes the affect of jitter and
makes it imperceptible in most applications. Applications that
are more likely to be sensitive to such degradation are those
requiring precise sensing of alternating magnetic elds; for
example, speed sensing of ring-magnet targets. For such applica-
tions, Allegro recommends its digital device families with lower
sensitivity to jitter. For more information on those devices,
contact your Allegro sales representative.
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