參數(shù)資料
型號(hào)： A1460A-1TQ176C
廠商： Microsemi SoC
文件頁數(shù)： 5/90頁
文件大?。?/td> 0K
描述： IC FPGA 6K GATES 176-TQFP
標(biāo)準(zhǔn)包裝： 40
系列： ACT™ 3
LAB/CLB數(shù)： 848
輸入/輸出數(shù)： 151
門數(shù)： 6000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 176-LQFP
供應(yīng)商設(shè)備封裝： 176-TQFP（24x24）
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 -5
Dedicated Clocks
Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed
performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad
Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the
array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by
special I/Os.
The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock
module (CLKMOD) that selects the source of the clock signal and may be driven as follows (Figure 2-6):
Externally from the CLKA pad
Externally from the CLKB pad
Internally from the CLKINA input
Internally from the CLKINB input
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal
clock track are located in each horizontal routing channel. The function of the clock module is determined
by the selection of clock macros from the macro library. The macro CLKBUF is used to connect one of
the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally
generated clock signal to a clock network. Since both clock networks are identical, the user does not care
whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like
resets, output enables, or data enables. This saves logic modules and results in performance increases
in some cases.
Routing Structure
The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O
modules. These routing tracks are metal interconnects that may either be of continuous length or broken
into segments. Segments can be joined together at the ends using antifuses to increase their lengths up
to the full length of the track.
Figure 2-6
Clock Networks
CLKB
CLKA
FROM
PADS
CLOCK
DRIVERS
CLKMOD
CLKINB
CLKINA
S0
S1
INTERNAL
SIGNAL
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
CLOCK TRACKS
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A1460A-1TQG176C 功能描述:IC FPGA 6K GATES 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
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