參數(shù)資料
型號: A1374EKB-T
廠商: Allegro Microsystems Inc
文件頁數(shù): 17/23頁
文件大?。?/td> 466K
描述: IC SENSOR HALL EFFECT PREC 3-SIP
產(chǎn)品培訓(xùn)模塊: Current Sensor
標(biāo)準(zhǔn)包裝: 500
傳感范圍: 1.75mV/G ~ 11.25mV/G
類型: 雙極或單極,可編程
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 10mA
電流 - 輸出(最大): 10mA
輸出類型: 模擬,比率
特點: 高精度
工作溫度: -40°C ~ 85°C
封裝/外殼: 3-SIP
供應(yīng)商設(shè)備封裝: 3-SIP
包裝: 散裝
High Precision, Output Pin Programmable
Linear Hall Effect Sensor ICs
A1373 and
A1374
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
V
PH
}
V
PM
}
V
PL
0
5
10
15
20
25
30
Time (約)
1    1  2  3
2  3  4  5  6  7  8  9  10
1
1
t
PLA
t
PMA
t
PME
t
PHE
Bitfield Select
(Code 10)
Register Select
(Code 3)
Mode Select
(Code 1)
Mode Select
(Code 1)
Bitfield Select
(Code 8)
Register Select
(Code 3)
Mode Select
(Code 2)
Blow Fuse
Bitfield Select
(Code 1)
Holding at V
PM
 is allowed when no
V
PL
 is required; dropping to V
PL
will increment by 1 bitfield
Register Select
(Code 0)
Mode Select
(Code 3)
Lock (blow Lock Bit fuse)
Bitfield Select
(Code 10)
Register Select
(Code 3)
V
OUT
 measurements
Mode Select
(Code 1)
Mode Select
(Code 1)
= Programming edge
Try Mode
selected
Try Mode
selected
Blow
Fuse
mode
selected
Sensitivity
Fine
register
selected
(Qvo Fine)
Sensitivity Fine selected
(Sensitivity Coarse)
10th address
selected
Bitfield 8
address
selected
Lock
Device
mode
selected
t
PLA
t
PMA
t
PME
t
PHE
t
PHP
0
5
10
15
20
25
30
Time (約)
Removing the output drive signal after each
 V
PM
allows measurement of the output pin
V
PH
}
V
PM
}
 m   r m nt
V
PL
3.0
2.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1    1  2  3
2  3  4  5  6  7  8  9  10
1
1
V
PH
}
V
PM
}
V
PL
0
5
10
15
20
25
30
Time (約)
1  2    1  2
1  2  3  4  5  6  7  8
3
0
5
10
15
20
25
30
Time (us)
V
PH
}
V
PM
}
oldin at
 i ll w wh n n
P
s requre ; roppn to
P
ill increment b 1 bitfiel
V
PL
1
1
1
2
3
The mid voltage range, V
PM
, is a neutral level used to separate
V
PH
 and V
PL
 pulses from each other.
The low level, V
PL
, pulse is used to increment the mode, register,
and bitfield addresses that are to be set. The device generates a
V
PL
 pulse on the falling edge of the mid-level to low-level transi-
tion, V
PM
 to V
PL
.
In Try Value mode,the programming drive signal can be held
at 5 V or less if no code search is required. If a code search is
required, then the output drive signal must be released to allow
the output level to be read for each bitfield increment (see panels
A and B, below).
To guarantee proper pulse recognition, each level must be held
for the predefined durations specified in the Programming Proto-
col Characteristics table. Failure to follow the specifications may
produce undefined results. Examples of common pulse trains are
shown in panels C and D, below.
A. Try Value Mode. Code search with drive signal held
at 5 V.
B. Try Value Mode. Code search with drive signal released
after each V
PM
, allows output to be measured after each code
increment.
C. Blow Fuse Mode: Code 8 / bit 4 is programmed.
D. Lock Device Mode. Device-level Lock Bit is programmed;
device programming is then permanently disabled.
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