參數(shù)資料
型號(hào): A1326LUA-T
元件分類: 磁阻傳感器
英文描述: MAGNETIC FIELD SENSOR-HALL EFFECT, RECTANGULAR, THROUGH HOLE MOUNT
封裝: 4 X 1.50 MM, 3 MM HEIGHT, LEAD FREE, SIP-3
文件頁數(shù): 10/11頁
文件大?。?/td> 277K
代理商: A1326LUA-T
Linear Hall Effect Sensor ICs with Analog Output
A1324, A1325,
and A1326
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Amp
Regulator
Clock/Logic
Hall Element
Tuned
Filter
Anti-Aliasing
LP Filter
Concept of Chopper Stabilization Technique
Typical Application Circuit
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative
to the offset that can be produced at the output of the Hall IC.
This makes it difficult to process the signal while maintaining an
accurate, reliable output over the specified operating temperature
and voltage ranges. Chopper stabilization is a unique approach
used to minimize Hall offset on the chip. Allegro employs a
patented technique to remove key sources of the output drift
induced by thermal and mechanical stresses. This offset reduc-
tion technique is based on a signal modulation-demodulation
process. The undesired offset signal is separated from the
magnetic field-induced signal in the frequency domain, through
modulation. The subsequent demodulation acts as a modulation
process for the offset, causing the magnetic field-induced signal
to recover its original spectrum at baseband, while the DC offset
becomes a high-frequency signal. The magnetic-sourced signal
then can pass through a low-pass filter, while the modulated DC
offset is suppressed. In addition to the removal of the thermal and
stress related offset, this novel technique also reduces the amount
of thermal noise in the Hall IC while completely removing the
modulated residue resulting from the chopper operation. The
chopper stabilization technique uses a high frequency sampling
clock. For demodulation process, a sample-and-hold technique
is used. This high-frequency operation allows a greater sampling
rate, which results in higher accuracy and faster signal-processing
capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling. This technique is made
possible through the use of a BiCMOS process, which allows the
use of low-offset, low-noise amplifiers in combination with high-
density logic integration and sample-and-hold circuits.
GND
1[1]
3[2]
Pin numbers in brackets
refer to the UA package
2[3]
VOUT
VOUT
A132x
VCC
V+
0.1 μF
CBYPASS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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