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參數(shù)資料
| 型號： | A1181EUA-T |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | Sensitive Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall-Effect Switches |
| 中文描述： | 敏感雙線現(xiàn)場可編程斬波穩(wěn)定單極霍爾效應(yīng)開關(guān) |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 356K |
| 代理商： | A1181EUA-T |
14
A1180-DS, Rev. 2
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
Allegro MicroSystems, Inc.
Sensitive Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switches
A1180/81/82/83
VPH
V+
t
VPM
VPL
0
Address 1
Address 2
Address n (
≤ 31)
Figure 8. Pulse sequence to select addresses
Falling edge of final BOP address digit
VPH
V+
t
VPM
VPL
0
Encode Lock Bit
Enable
Address
Blow
32 pulses
Figure 9. Pulse sequence to encode lock bit
Lock Bit Programming.
After the desired BOP calibration value
is programmed, and all of the corresponding biteld-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (biteld address 32) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bitelds, as shown in gure 9.
Address Selection
.
After addressing mode is enabled, the
target biteld address, is indicated by a series of VPM pulses, as
shown in gure 8.
Figure 7. Addressing mode enable pulse sequence
VPH
V+
t
VPM
VPL
0
Enabling Addressing Mode
.
The rst segment of code is a
keying sequence used to enable the biteld addressing mode. As
shown in gure 7, this segment consists of one short VPH pulse,
one VPM pulse, and one short VPH pulse, with no supply inter-
ruptions. This sequence is designed to prevent the device from
being programmed accidentally, such as by noise on the supply
line.
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| A1181LLHLT | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:Sensitive Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall-Effect Switches |
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| A1181LUA-T | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:Sensitive Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall-Effect Switches |
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