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參數(shù)資料
| 型號： | A1180LUA-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 543K |
| 描述： | IC SWITCH HALL EFFECT UNI 3-SIP |
| 產(chǎn)品培訓(xùn)模塊： | Current Sensor |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 傳感范圍： | 60G ~ 200G 跳閘 - 可編程，固定釋放 |
| 類型： | 單極開關(guān) |
| 電源電壓： | 3.5 V ~ 24 V |
| 電流 - 電源： | 5mA |
| 輸出類型： | 數(shù)字，開路集電極 |
| 特點： | 可編程 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 3-SIP |
| 供應(yīng)商設(shè)備封裝： | 3-SIP |
| 包裝： | 散裝 |
Sensitive Two-Wire Field-Programmable
Chopper-Stabilized Unipolar Hall Effect Switches
A1180, A1181,
A1182, and A1183
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The pulse sequences consist of the following groups of pulses:
1. An enable sequence.
2. A bit eld address sequence.
3. When permanently setting the bit eld, a long V
PH
fuse-blow-
ing pulse. (Note: Blown bit fuses cannot be reset.)
4. When permanently setting the bit eld, the level of V
CC
must
be allowed to drop to zero between each pulse sequence, in
order to clear all registers. However, when provisionally set-
ting bit elds, V
CC
must be maintained at V
PL
between pulse
sequences, in order to maintain the prior bit eld settings while
preparing to set additional bit elds.
Bit elds that are not set are evaluated as zeros. The bit eld-level
fuses for 0 value bit elds are never blown. This prevents inad-
vertently setting the bit eld to 1. Instead, blowing the device-
level fuse protects the 0 bit elds from being accidentally set in
the future.
When provisionally trying the calibration value, one pulse
sequence is used, using decimal values. The sequence for setting
the value 5
10
is shown in gure 5.
When permanently setting values, the bit elds must be set indi-
vidually, and 5
10
must be programmed as binary 101. Bit 3 is
set to 1 (000100
2
, which is 4
10
), then bit 1 is set to 1 (000001
2
,
which is 1
10
). Bit 2 is ignored, and so remains 0.Two pulse
sequences for permanently setting the calibration value 5 are
shown in gure 6. The nal V
PH
pulse is maintained for a longer
period, enough to blow the corresponding bit eld-level fuse.
V
PH
V+
t
V
PM
V
PL
0
Encode 00100
2
(4
10
)
Enable
Address
Address
Blow
Blow
Enable
Encode 00001
2
(1
10
)
Figure 6. Pulse sequence to permanently encode calibration value 5 (101 binary, or
bit eld address 3 and bit eld address 1).
V
PH
V+
t
V
PM
V
PL
0
Try 5
10
Enable
Address
Clear
Optional
Monitoring
Figure 5. Pulse sequence to provisionally try calibration value 5.
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