jc
參數(shù)資料
型號(hào)： A1020B-VQ80I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 3/98頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 2K GATES 80-VQFP IND
標(biāo)準(zhǔn)包裝： 90
系列： ACT™ 1
LAB/CLB數(shù)： 547
輸入/輸出數(shù)： 69
門數(shù)： 2000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-TQFP
供應(yīng)商設(shè)備封裝： 80-VQFP（14x14）
11
Hi R e l F P GA s
P ack ag e Th er m a l Ch ar ac t e r i st i c s
The device junction to case thermal characteristic is
θ
jc, and
the junction to ambient air characteristic is
θ
ja. The thermal
characteristics for
θ
ja are shown with two different air flow
rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a CPGA 176-pin package at military
temperature is as follows:
P o w e r D i ss ip a t io n
Gener al P o w e r E quat i o n
P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N +
IOH * (VCC – VOH) * M
where:
ICCstandby is the current flowing when no inputs or outputs
are changing.
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL.
M equals the number of outputs driving TTL loads to
VOH.
Accurate values for N and M are difficult to determine
because they depend on the family type, on the design, and on
the system I/O. The power can be divided into two
components—static and active.
S tat i c P o w e r Co m ponen t
Actel FPGAs have small static power components that result
in power dissipation lower than that of PALs or PLDs. By
integrating multiple PALs or PLDs into one FPGA, an even
greater reduction in board-level power dissipation can be
achieved.
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst-case conditions.
The static power dissipated by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this value is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all
outputs driving low, and 140 mW with all outputs driving high.
Ac ti v e P ower Com p o nent
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the external
I/O. Active power dissipation results from charging internal
chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external
capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is
the totempole current in CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance that
Package Type
Pin Count
θ
jc
θ
ja
Still Air
θ
ja
300 ft/min
Units
Ceramic Pin Grid Array
84
132
133
176
207
257
6.0
4.8
4.6
3.5
2.8
33
25
23
21
15
20
16
15
12
10
8
°C/W
Ceramic Quad Flat Pack
84
132
172
196
256
7.8
7.2
6.8
6.4
6.2
40
35
25
23
20
30
25
20
15
10
°C/W
Max. junction temp. (°C) – Max. military temp.
θ
ja (°C/W)
------------------------------------------------------------------------------------------------------------------
150°C – 125°C
23°C/W
------------------------------------
1.1 W
==
Family
ICC
VCC
Power
ACT 3
2 mA
5.25V
10.5 mW
1200XL/3200DX
2 mA
5.25V
10.5 mW
ACT 2
2 mA
5.25V
10.5 mW
ACT 1
3 mA
5.25V
15.8 mW
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