(Wor s t - C as e M i l i t a r y Cond i t i o n s , V CC <" />
參數(shù)資料
型號(hào): A1020B-1PL68C
廠商: Microsemi SoC
文件頁數(shù): 43/98頁
文件大小: 0K
描述: IC FPGA 2K GATES 68-PLCC COM
標(biāo)準(zhǔn)包裝: 19
系列: ACT™ 1
LAB/CLB數(shù): 547
輸入/輸出數(shù): 57
門數(shù): 2000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24.23x24.23)
48
A3 21 00 DX Ti m i n g Ch ar ac te r i st i c s
(Wor s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Combinatorial Functions
tPD
Internal Array Module Delay
3.1
4.1
ns
tPDD
Internal Decode Module Delay
3.3
4.3
ns
Logic Module Predicted Routing Delays1
tRD1
FO=1 Routing Delay
1.3
1.8
ns
tRD2
FO=2 Routing Delay
1.9
2.6
ns
tRD3
FO=3 Routing Delay
2.6
3.4
ns
tRD4
FO=4 Routing Delay
3.3
4.3
ns
tRD5
FO=8 Routing Delay
0.6
0.8
ns
tRDD
Decode-to-Output Routing Delay
0.5
0.6
ns
Logic Module Sequential Timing
tCO
Flip-Flop Clock-to-Output
3.1
4.1
ns
tGO
Latch Gate-to-Output
3.1
4.1
ns
tSU
Flip-Flop (Latch) Setup Time
0.5
0.6
ns
tH
Flip-Flop (Latch) Hold Time
0.0
ns
tRO
Flip-Flop (Latch) Reset to Output
3.1
4.1
ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.9
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
4.3
5.8
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
5.6
7.5
ns
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
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