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參數(shù)資料
| 型號： | A1010B-2PQG100I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 4/98頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1200 GATES 100-PQFP IND |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | ACT™ 1 |
| LAB/CLB數(shù)： | 295 |
| 輸入/輸出數(shù)： | 57 |
| 門數(shù)： | 1200 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
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can be combined with frequency and voltage to represent
active power dissipation.
E qui v a l ent C apac i t ance
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
Power (uW) = CEQ * VCC
2 * F
(1)
where:
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements are made over a range
of frequencies at a fixed value of VCC. Equivalent capacitance
is frequency independent so that the results can be used over
a wide range of operating conditions. Equivalent capacitance
values are shown below.
CE Q Val ues f o r Act e l FP G A s
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piecewise linear summation
over all components that applies to all ACT 1, 1200XL,
3200DX, ACT 2, and ACT 3 devices. Since the ACT 1 family has
only one routed array clock, the terms labeled routed_Clk2,
dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2
family has two routed array clocks, and the dedicated_Clk
and IO_Clk terms do not apply. For ACT 3 devices, all terms
will apply.
Power = VCC
2 * [(m * C
EQM* fm)modules + (n * CEQI* fn)inputs +
(p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1
+ (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 +
(r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk +
(s2 * CEQCI * fs2)IO_Clk](2)
where:
CEQ
= Equivalent capacitance in pF
VCC
= Power supply in volts (V)
F
= Switching frequency in MHz
ACT 3
1200XL
3200DX ACT 2 ACT 1
Modules (CEQM)
6.7
5.2
5.8
3.7
Input Buffers (CEQI)
7.2
11.6
12.9
22.1
Output Buffers (CEQO)
10.4
23.8
31.2
Routed Array Clock
Buffer Loads (CEQCR)
1.6
3.5
3.9
4.6
Dedicated Clock Buffer
Loads (CEQCD)
0.7
N/A
I/O Clock Buffer Loads
(CEQCI)
0.9
N/A
m
= Number of logic modules switching at fm
n
= Number of input buffers switching at fn
p
= Number of output buffers switching at fp
q1
= Number of clock loads on the first routed
array clock (all families)
q2
= Number of clock loads on the second routed
array clock (ACT 2, 1200XL, 3200DX, ACT 3
only)
r1
= Fixed capacitance due to first routed array
clock (all families)
r2
= Fixed capacitance due to second routed array
clock (ACT 2, 1200XL, 3200DX, ACT 3 only)
s1
= Fixed number of clock loads on the dedicated
array clock (ACT 3 only)
s2
= Fixed number of clock loads on the dedicated
I/O clock (ACT 3 only)
CEQM
= Equivalent capacitance of logic modules in pF
CEQI
= Equivalent capacitance of input buffers in pF
CEQO
= Equivalent capacitance of output buffers
in pF
CEQCR
= Equivalent capacitance of routed array clock
in pF
CEQCD
= Equivalent capacitance of dedicated array
clock in pF
CEQCI
= Equivalent capacitance of dedicated I/O clock
in pF
CL
= Output lead capacitance in pF
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
fp
= Average output buffer switching rate in MHz
fq1
= Average first routed array clock rate in MHz
(all families)
fq2
= Average second routed array clock rate in
MHz (ACT 2, 1200XL, 3200DX, ACT 3 only)
fs1
= Average dedicated array clock rate in MHz
(ACT 3 only)
fs2
= Average dedicated I/O clock rate in MHz
(ACT 3 only)
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| A1010B-2VQ80C | 功能描述:IC FPGA 1200 GATES 80-VQFP COM RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 1 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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