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參數(shù)資料
| 型號： | A1010B-1VQ80C |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 52/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1200 GATES 80-VQFP COM |
| 標準包裝： | 90 |
| 系列： | ACT™ 1 |
| LAB/CLB數(shù)： | 295 |
| 輸入/輸出數(shù)： | 57 |
| 門數(shù)： | 1200 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 80-TQFP |
| 供應(yīng)商設(shè)備封裝： | 80-VQFP（14x14） |
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56
Pi n D e s c ri pt i o n
CLK
Clock (Input)
ACT 1 only. TTL Clock input for global clock distribution
network. The Clock input is buffered prior to clocking the
logic modules. This pin can also be used as an I/O.
CLKA
Clock A (Input)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for
global clock distribution networks. The Clock input is
buffered prior to clocking the logic modules. This pin can also
be used as an I/O.
CLKB
Clock B (Input)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for
global clock distribution networks. The Clock input is
buffered prior to clocking the logic modules. This pin can also
be used as an I/O.
DCLK
Diagnos ti c Clo ck (Input)
TTL
Clock
input
for
diagnostic
probe
and
device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-wired) A rray
Clock (Input)
ACT 3 only. TTL Clock input for sequential modules. This
input is directly wired to each S-module and offers clock
speeds independent of the number of S-modules being driven.
This pin can also be used as an I/O.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, tristate, or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. In the ACT 3 and
3200DX families, unused I/Os are automatically tri-stated.
With this configuration, the input buffer internal to the I/O
module is disabled. In the ACT 1, ACT 2 and 1200XL families,
unused I/Os are automatically configured as bi-directional
buffers where each buffer is configured as a LOW driver.
IOCLK
Dedicated (Hard-wired) I/O
Clock (Input)
ACT 3 only. TTL Clock input for I/O modules. This input is
directly wired to each I/O module and offers clock speeds
independent of the number of I/O modules being driven. This
pin can also be used as an I/O.
IOPCL
Dedicated (Hard-wired) I/O
Prese t/Clear (Input)
ACT 3 only. TTL input for I/O preset or clear. This global input
is directly wired to the preset and clear inputs of all I/O
registers. This pin functions as an I/O when no I/O preset or
clear macros are used.
MODE
Mode (In put)
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/Os. To provide debugging capability, the MODE
pin should be terminated to GND through a 10 k
resistor so
that the MODE pin can be pulled high when required.
NC
No C onnecti on
This pin is not connected to circuitry within the device.
PRA, I/O
Prob e A (Output)
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
PRB, I/O
Prob e B (Output)
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
SDI
Seri al Data Input (Input)
Serial
data
input
for
diagnostic
probe
and
device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
V CC
5.0 V Supply Vol tage
HIGH supply voltage.
QCLKA/B, C,D Quadrant Clock (Input/Output)
3200DX only. These four pins are the quadrant clock inputs.
When not used as a register control signal, these pins can
function as general purpose I/O.
TCK
Test Clock
Clock signal to shift the JTAG data into the device. This pin
functions as an I/O when the JTAG fuse is not programmed.
JTAG pins are only available in the 3200DX device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A1010B-1VQ80I | 功能描述:IC FPGA 1200 GATES 80-VQFP IND RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 1 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A1010B-1VQ84B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ACT 1 Series FPGAs |
| A1010B-1VQ84C | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ACT 1 Series FPGAs |
| A1010B-1VQ84I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ACT 1 Series FPGAs |
| A1010B-1VQ84M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ACT 1 Series FPGAs |
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