參數(shù)資料
型號： 9TCS1082NLGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC32
封裝： 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-32
文件頁數(shù)： 25/28頁
文件大小： 376K
代理商： 9TCS1082NLGI
9TCS1082
MOBILE ACCESS—CLOCK SYNTHESIZER & TEMPERATURE SENSOR FOR PORTABLE DEVICES
SYNTHESIZERS
IDT MOBILE ACCESS—CLOCK SYNTHESIZER & TEMPERATURE SENSOR FOR PORTABLE DEVICES
6
9TCS1082
REV 0.4 100411
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9TCS1082. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–SMBus Interface
AC Electrical Characteristics–Input/Common Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Maximum Supply Voltage
VDDxxx
Core/Logic Supply
3.6
V
1,2
Maximum Supply Voltage
VDDIOxxx
Core/Logic Supply
3.6
V
1,2
Maximum Input Voltage
VIH
3.3V LVCMOS Inputs
3.6
V
1,2,3
Minimum Input Voltage
VIL
Any Input
GND - 0.5
V
Storage Temperature
Ts
-
-65
150
°C
1,2
Case Temperature
Tcase
-
115
°C
1,2
1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied, nor guaranteed.
3 Maximum input voltage is not to exceed maximum VDD
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
SMBus Voltage
VDD
2.7
3.6
V
1
Low-level Output Voltage
VOLSMB
@ IPULLUP
0.4
V
1
Current sinking at
VOLSMB = 0.4 V
IPULLUP
SMB Data Pin
4
mA
1
SCLK/SDATA
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
Maximum SMBus Operating
Frequency
FSMBUS
Block Mode
400
kHz
1
1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Clk Stabilization
TSTAB
From VDD Power-Up or de-
assertion of PD# to 1st clock
1.8
ms
1
Tdrive_PD#
TDRPD
Differential output enable after
PD# de-assertion
300
us
1
1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.
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