參數(shù)資料
型號(hào): 9LRS3187BKLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC32
封裝: ROHS COMPLIANT, PLASTIC, MLF-32
文件頁(yè)數(shù): 12/20頁(yè)
文件大小: 193K
代理商: 9LRS3187BKLF
IDT Programmable Timing Control Hub for Intel Based Systems
1602E—04/29/11
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
2
Datasheet
Pin Description
Pin# Pin Name
Type Pin Description
1
VDDDOT96MHz_3.3
PWR Power pin for the 96MHz output 3.3V.
2
GNDDOT96MHz
PWR Ground pin for the 96MHz output
3
DOT96T_LPR
OUT
True DOT96 output with integrated 33ohm series resistor. No
50ohm resistor to GND needed.
4
DOT96C_LPR
OUT
Complement DOT96 output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
5
VDD_27MHz
PWR Power pin for the 27MHz output 3.3V.
6
27MHz_nonSS
OUT
3.3V Single-ended 27MHz non-spread clock.
7
27MHz_SS
OUT
3.3V Single-ended 27MHz spread clock.
8
GND27MHz
OUT
Ground pin for the 27MHz outputs.
9
GNDSATA
PWR Ground pin for the SATA outputs.
10
SATAT_LPR
OUT
True clock of differential 0.8V push-pull SATA/SRC output with
integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
11
SATAC_LPR
OUT
Complementary clock of differential 0.8V push-pull SATA/SRC
output with integrated 33ohm series resistor. No 50ohm resistor
to GND needed.
12
GNDSRC
PWR Ground pin for the SRC outputs
13
SRCT1_LPR
OUT
True clock of differential 0.8V push-pull SRC output with
integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
14
SRCC1_LPR
OUT
Complementary clock of differential 0.8V push-pull SRC output
with integrated 33ohm series resistor. No 50ohm resistor to
GND needed.
15
VDDSRC_IO
PWR 1.05V to 3.3V from external power supply
16
*CPU_STOP#
IN
Stops all CPU clocks, except those set to be free running
clocks
17
VDDSRC_3.3
PWR Supply for SRC clocks, 3.3V nominal
18
VDDCPU_IO
PWR 1.05V to 3.3V from external power supply
19
CPUC1_LPR
OUT
Complementary clock of differential pair 0.8V push-pull CPU
outputs with integrated 33ohm series resistor. No 50 ohm
resistor to GND needed.
20
CPUT1_LPR
OUT
True clock of differential pair 0.8V push-pull CPU outputs with
integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
21
GNDCPU
PWR Ground pin for the CPU outputs.
22
CPUC0_LPR
OUT
Complementary clock of differential pair 0.8V push-pull CPU
outputs with integrated 33ohm series resistor. No 50 ohm
resistor to GND needed.
23
CPUT0_LPR
OUT
True clock of differential pair 0.8V push-pull CPU outputs with
integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
24
VDDCPU_3.3
PWR Supply for CPU clocks, 3.3V nominal
25
CLKPWRGD/PD#_3.3
IN
Notifies CK505 to sample latched inputs, or PWRDWN# mode
26
GNDREF
PWR Ground pin for the REF outputs.
27
X2
OUT
Crystal output, Nominally 14.318MHz
28
X1
IN
Crystal input, Nominally 14.318MHz
29
VDDREF_3.3
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
30
REF_2/FSLC_3.3**
I/O
14.318 MHz reference clock, which can drive 2 loads / 3.3V
tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
31
SDATA_3.3
I/O
Data pin for SMBus circuitry, 3.3V tolerant
32
SCLK_3.3
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
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