參數(shù)資料
型號: 9LPRS436CKLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQCC48
封裝: 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48
文件頁數(shù): 14/20頁
文件大?。?/td> 195K
代理商: 9LPRS436CKLF
IDT
Low Power Clock for Intel Atom-Based Systems
1561C — 08/24/11
9LPRS436C
Low Power Clock for Intel Atom
-Based Systems
3
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
**FS3/12_288M_2x
I/O
Frequency select latch input pin / 12.288MHz output, 3.3V
2
VDD12_288
PWR
Power for 12.288MHz PLL and output buffer, nominal 3.3V.
3PEREQ1#
IN
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the SMBus. 1 = selected outputs are disabled, 0 = selected
outputs are enabled.
4PEREQ2#
IN
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the SMBus. 1 = selected outputs are disabled, 0 = selected
outputs are enabled.
5
**FS4/PCICLK0_2x
I/O
Frequency select latch input pin / 3.3V PCI clock output.
6
GND
PWR
Ground pin.
7
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
8
**ITP_EN/PCICLK_F0_2x
I/O
ITP Enable Latched Input/Free Running PCI clock output.
ITP_Enable Selects the functionality of the CPU_ITP/SRC output as follows:
1 = CPU_ITP output
0 = SRC output
9PEREQ3#
IN
Real-time input pin that controls PCIEXCLK outputs that are selected through
the SMBus. 1 = selected outputs are disabled, 0 = selected outputs are
enabled.
10
*SEL12_48#/12_48MHz_2x
I/O
Latched select input for 12/48MHz output. 1=12MHz, 0=48MHz. 12/48MHz
clock output.
11
VDD
PWR
Power supply, nominal 3.3V
12
FSLA/USB48_2x
I/O
3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs,
see input electrical characteristics for Vil_FS and Vih_FS values. / 48.00MHz
USB clock
13
GND
PWR
Ground pin.
14
DOTT_96MHzLR
OUT
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
to GND needed. No Rs needed.
15
DOTC_96MHzLR
OUT
Complementary clock of low power differential pair for 96.00MHz DOT clock.
No 50ohm resistor to GND needed. No Rs needed.
16
FSLB
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
17
GNDSATA
PWR
Ground pin for the SATA outputs
18
SATAT_LR/PCIeT_LR3
OUT
True clock of differential SATA pair. / True clock of differential PCI-Express pair
- selectable by FS(4:3) ; both are 0.8V differential push pull outputs with
integrated 33ohm series resistor.
19
SATAC_LR/PCIeC_LR3
OUT
Complementary clock of differential SATA pair. / Complementary clock of
differential PCI-Express pair - selectable by FS(4:3); both are 0.8V differential
push pull outputs with integrated 33ohm series resistor.
20
VDDSATA
PWR
Supply for SATA clocks, 3.3V nominal
21
PCIeT_LR0
OUT
True clock of 0.8V differential push-pull PCI_Express pair with integrated
33ohm series resistor
22
PCIeC_LR0
OUT
Complementary clock of 0.8V differential push-pull PCI_Express pair with
integrated 33ohm series resistor
23
PCIeT_LR1
OUT
True clock of 0.8V differential push-pull PCI_Express pair with integrated
33ohm series resistor
24
PCIeC_LR1
OUT
Complementary clock of 0.8V differential push-pull PCI_Express pair with
integrated 33ohm series resistor
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