參數(shù)資料
型號: 9FG104DGILF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28
文件頁數(shù): 17/17頁
文件大小: 161K
代理商: 9FG104DGILF
IDT
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
9
SMBus Table: Frequency Select Readback Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
SEL14M_25M#1
(FS3)
State of pin 17
R
Pin 17
Bit 6
FS21
State of pin 6
R
Pin 6
Bit 5
FS11
State of pin 24
R
Pin 24
Bit 4
FS01
State of pin 25
R
Pin 25
Bit 3
SPREAD1
State of pin 26
R
Off
On
Pin 16
Bit 2
0
Bit 1
0
Bit 0
0
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
RID3
R
-
X
Bit 6
RID2
R
-
X
Bit 5
RID1
R
-
X
Bit 4
RID0
R
-
X
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
SMBus Table: DEVICE ID
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
DID7
R
-
0
Bit 6
DID6
R
-
0
Bit 5
DID5
R
-
0
Bit 4
DID4
R
-
0
Bit 3
DID3
R
-
1
Bit 2
DID2
R
-
0
Bit 1
DID1
R
-
0
Bit 0
DID0
R
-
0
SMBus Table: Byte Count Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
BC7
RW
-
0
Bit 6
BC6
RW
-
0
Bit 5
BC5
RW
-
0
Bit 4
BC4
RW
-
0
Bit 3
BC3
RW
-
0
Bit 2
BC2
RW
-
1
Bit 1
BC1
RW
-
1
Bit 0
BC0
RW
-
1
Byte 6
Writing to this register will
configure how many bytes will
be read back, default is 07 = 7
bytes.
-
Byte 5
-
Byte 4
-
REVISION ID
-
16
VENDOR ID
-
45
44
See Frequency Selection Table,
Page 1
6
27
Reserved
Device ID = 08 hex
Byte 3
相關PDF資料
PDF描述
9FG104DFILFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
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