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參數(shù)資料
| 型號： | 9DBL411AGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO20 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 88K |
| 代理商： | 9DBL411AGLFT |
IDTTM Four Output Differential Buffer for PCI Express
1250B—02/21/08
Advance Information
ICS9DBL411A
Four Output Differential Buffer for PCI Express
6
AC Electrical Characteristics - DIF Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
NOTES
Rising Edge Slew Rate
t
SLR
Differential Measurement
1
2.5
V/ns
1,2
Falling Edge Slew Rate
t
FLR
Differential Measurement
1
2.5
V/ns
1,2
Slew Rate Variation
t
SLVAR
Single-ended Measurement
20
%
1
Maximum Output Voltage
V
HIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
V
LOW
Includes undershoot
-300
mV
1
Differential Voltage Swing
V
SWING
Differential Measurement
1200
mV
1
Crossing Point Voltage
V
XABS
Single-ended Measurement
300
mV
1,3,4
Crossing Point Variation
V
XABSVAR
Single-ended Measurement
140
mV
1,3,5
D
CYCDIS0
Differential Measurement,
fIN<=100MHz
0.5
%
1,6
D
CYCDIS1
Differential Measurement
100MHz < fIN<=267MHz
+5
%
1,6
D
CYCDIS2
Differential Measurement,
fIN>267MHz
+7
%
1,6
DIF Jitter - Cycle to Cycle
DIFJ
C2C
Differential Measurement,
Additive
25
ps
1
DIF[3:0] Skew
DIF
SKEW
Differential Measurement
50
ps
1
Propagation Delay
t
PD
Input to output Delay
2.5
3.5
ns
1
PCIe Gen2 Phase Jitter -
Addtive
t
phase_addHI
1.5MHz < fIN < Nyquist (50MHz)
0.8
ps rms
1
PCIe Gen2 Phase Jitter -
Addtive
t
phase_addLO
10KHz < fIN < 1.5MHz
0.1
ps rms
1
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
8 Maximum input voltage is not to exceed maximum VDD
6 Tthis is the figure refers to the maximum distortion of the input wave form.
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and
falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
7 Operation under these conditions is neither implied, nor guaranteed.
Duty Cycle Distortion
相關PDF資料 |
PDF描述 |
|---|---|
| 9DBL411AKLFT | LOW SKEW CLOCK DRIVER, PQCC20 |
| 9DBL411AGLF | LOW SKEW CLOCK DRIVER, PDSO20 |
| 9DBL411BKILF | LOW SKEW CLOCK DRIVER, PQCC20 |
| 9DBL411BGILF | LOW SKEW CLOCK DRIVER, PDSO20 |
| 9DBL411BGILFT | LOW SKEW CLOCK DRIVER, PDSO20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 9DBL411AKLF | 功能描述:時鐘緩沖器 4 OUTPUT PCIE BUFFER LOW POWER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411AKLFT | 功能描述:時鐘緩沖器 4 OUTPUT PCIE BUFFER LOW POWER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411B | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI |
| 9DBL411BGILF | 功能描述:時鐘緩沖器 LOW POWER PCIE/QPI w /POWER DOWN FEATURE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411BGILFT | 功能描述:時鐘緩沖器 LOW POWER PCIE/QPI w /POWER DOWN FEATURE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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