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參數(shù)資料
| 型號： | 9DBL411AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO20 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 88K |
| 代理商： | 9DBL411AGLF |
IDTTM Four Output Differential Buffer for PCI Express
1250B—02/21/08
Advance Information
ICS9DBL411A
Four Output Differential Buffer for PCI Express
4
MLF Pin Description
PIN #
(MLF)
PIN NAME
PIN TYPE
DESCRIPTION
1
VDDA
PWR
3.3V Power for the Analog Core
2
GNDA
GND
Ground for the Analog Core
3OE3#
IN
Output Enable for DIF3 output. Control is as follows:
0 = enabled, 1 = Low-Low
4DIF3C_LPR
OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
5
DIF3T_LPR
OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
6
VDD_IO
PWR
Power supply for low power differential outputs, nominal 1.05V to 3.3V
7
GND
Ground pin
8DIF2C_LPR
OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
9
DIF2T_LPR
OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
10
OE2#
IN
Output Enable for DIF2 output. Control is as follows:
0 = enabled, 1 = Low-Low
11
DIF1C_LPR
OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
12
DIF1T_LPR
OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
13
OE1#
IN
Output Enable for DIF1 output. Control is as follows:
0 = enabled, 1 = Low-Low
14
GND
Ground pin
15
VDD_IO
PWR
Power supply for low power differential outputs, nominal 1.05V to 3.3V
16
DIF0C_LPR
OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
17
DIF0T_LPR
OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
18
OE0#
IN
Output Enable for DIF0 output. Control is as follows:
0 = enabled, 1 = Low-Low
19
DIF_INC
IN
Complement side of differential input clock
20
DIF_INT
IN
True side of differential input clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DBL411BKILF | LOW SKEW CLOCK DRIVER, PQCC20 |
| 9DBL411BGILF | LOW SKEW CLOCK DRIVER, PDSO20 |
| 9DBL411BGILFT | LOW SKEW CLOCK DRIVER, PDSO20 |
| 9DBL411BKLF | LOW SKEW CLOCK DRIVER, PQCC20 |
| 9DBL411BGLFT | LOW SKEW CLOCK DRIVER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DBL411AGLFT | 功能描述:時鐘緩沖器 4 OUTPUT PCIE BUFFER LOW POWER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411AKLF | 功能描述:時鐘緩沖器 4 OUTPUT PCIE BUFFER LOW POWER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411AKLFT | 功能描述:時鐘緩沖器 4 OUTPUT PCIE BUFFER LOW POWER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411B | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI |
| 9DBL411BGILF | 功能描述:時鐘緩沖器 LOW POWER PCIE/QPI w /POWER DOWN FEATURE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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