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參數(shù)資料
| 型號： | 9DB833AGILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | ROHS COMPLIANT, TSSOP-48 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 226K |
| 代理商： | 9DB833AGILF |
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
8
9DB833
REV C 052411
Electrical Characteristics–PCIe Phase Jitter Parameters
Clock Periods Differential Outputs Tracking Spread Spectrum
Clock Periods Differential Outputs not Tracking Spread Spectrum
TA = TCOM or TI ND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
tjphPCIeG1
PCIe Gen 1
30
86
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.0
3
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MH z)
2.2
3.1
ps
(rms)
1,2
tjphPCIeG3
PC Ie Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.5
1
ps
(rms)
1,2,4
t
jphPC IeG1
PCIe Gen 1
1
5
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MH z)
0.2
0.3
ps
(rms)
1,2
t
jphPC IeG3
PC Ie Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.0
0.1
ps
(rms)
1,2,4
1 Applies to all outputs.
4 Subject to final radification by PCI SIG.
tjphPCIeG2
2
See http://www.pcisig.com for complete specs
tjphPCIeG2
Phase Jitter, PLL Mode
Additive Phase Jitter, Bypass
Mode
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
1 Clock
1us
0.1s
1us
1 Clock
Lg-
-SSC
-ppm error
0ppm
+ ppm error
+SSC
Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal
Maximum
9.949
9.999
10.024
10.025
10.026
10.051
10.101
ns
1,2,3
Notes
Definition
Units
Measurement
Window
Symbol
DIF 100
1 Clock
1us
0.1s
1us
1 Clock
Lg-
-SSC
-ppm error
0ppm
+ ppm error
+SSC
Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal
Maximum
DIF
100M
9.949
9.999
10.000
10.001
10.051
ns
1,2,3
1Guaranteed by desig n and characterization, not 100% tested in production.
3 Driven by PCIe output of main clock, PLL Mode or Bypass mode
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+ accuracy requirements. The
buffer itself does not contribute to ppm error.
Notes
Measurement
Window
Units
Symbol
Definition
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB833AGILFT | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB833AGLF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB833AGLFT | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL0242BKILF | 功能描述:IC CLK FANOUT/BUFF ZD 24VFQFPN 制造商:idt, integrated device technology inc 系列:- 包裝:托盤 零件狀態(tài):在售 PLL:是 主要用途:PCI Express（PCIe） 輸入:HCSL 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:是/是 頻率 - 最大值:200MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商器件封裝:24-VFQFPN（4x4） 標(biāo)準(zhǔn)包裝:490 |
| 9DBL0252BKILF | 功能描述:CLOCK BUFFER 3.3V LP-HCSL PCIE 制造商:idt, integrated device technology inc 系列:* 包裝:托盤 零件狀態(tài):在售 PLL:是 主要用途:PCI Express（PCIe） 輸入:HCSL 輸出:HCSL 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:是/是 頻率 - 最大值:200MHz 電壓 - 電源:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商器件封裝:24-VFQFPN（4x4） 標(biāo)準(zhǔn)包裝:490 |
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