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參數(shù)資料
| 型號： | 9DB833AFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | ROHS COMPLIANT, SSOP-48 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 226K |
| 代理商： | 9DB833AFLFT |
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
7
9DB833
REV C 052411
Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Slew rate
Trf
Scope averaging on
1
2
4
V/ns
1, 2, 3
Slew rate matching
ΔTrf
Slew rate matching, Scope averaging on
20
%
1, 2, 4
Voltage High
VHigh
660
800
850
1
Voltage Low
VLow
-150
150
1
Max Voltage
Vmax
1150
1
Min Voltage
Vmin
-300
1
Vsw ing
Vswing
Scope averaging off
300
mV
1, 2
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
250
550
mV
1, 5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
140
mV
1, 6
2 Measured from differential waveform
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope averaging
on)
Measurement on single ended signal using absolute
value. (Scope averaging off)
mV
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R). Fo r RR = 475 (1%), IREF = 2. 32mA. IOH =
6 x I
REF and VOH = 0.7 V @ ZO=50 (100 different ial im peda nce).
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
TA = TCOM or TI ND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
-3dB point in High BW Mode
2
2.7
4
MHz
1
-3dB point in Low BW Mode
0.7
1.1
1.4
MHz
1
PLL Jitter Peaking
t
JPEAK
Peak Pass band Gain
1.5
2
dB
1
Duty C ycle
t
DC
Measured differentially, PLL Mode
45
49
55
%
1
Duty Cycle D istortion
tDCD
Measured differentially, Bypass Mode @100MH z
-2
2
%
1,4
tpdBYP
Bypass Mode, VT = 50%
2500
4500/
4900
ps
1,5
t
pdPLL
PLL Mode V
T =
50%
-250
-50
250
ps
1
Skew, Output to Output
tsk3
VT = 50%
50/60
ps
1,5
PLL mode
50
ps
1,3
Additive Jitter in Bypass Mode
50
ps
1,3
1Guaranteed by design and characterization, not 100% tested in production.
2 I
REF = VDD /(3xRR). For RR = 475 (1%), IREF = 2.3 2mA . IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .
3 Measured from differential waveform
4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
5 First number is commercial temp, second number is industrial temp.
Skew, Input to Output
Jitter, Cycle to cycle
tjcyc-cyc
PLL Bandwidth
BW
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