參數(shù)資料
型號(hào): 9DB823BGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
文件頁(yè)數(shù): 6/21頁(yè)
文件大?。?/td> 185K
代理商: 9DB823BGLFT
IDT
Eight Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1444E - 05/09/11
9DB823B
Eight Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
14
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PD_Mode
PD# drive mode
RW
driven
Hi-Z
0
Bit 6
STOP_Mode
DIF_Stop# drive mode
RW
driven
Hi-Z
0
Bit 5
PD_Polarity
Select PD polarity
RW
Low
High0
Bit 4
Reserved
RW
X
Bit 3
BYPASS#1
BYPASS#/PLL1
RW
Input
Bit 2
PLL_BW#
Select PLL BW
RW
High BW
Low BW
1
Bit 1
BYPASS#0
BYPASS#/PLL0
RW
Input
Bit 0
SRC_DIV#
SRC Divide by 2 Select
RW
x/2
x/1
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
DIF_7
Output Enable
RW
Disable
Enable
1
Bit 6
DIF_6
Output Enable
RW
Disable
Enable
1
Bit 5
DIF_5
Output Enable
RW
Disable
Enable
1
Bit 4
DIF_4
Output Enable
RW
Disable
Enable
1
Bit 3
DIF_3
Output Enable
RW
Disable
Enable
1
Bit 2
DIF_2
Output Enable
RW
Disable
Enable
1
Bit 1
DIF_1
Output Enable
RW
Disable
Enable
1
Bit 0
DIF_0
Output Enable
RW
Disable
Enable
1
NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!
SMBus Table: OE Pin Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
DIF_7
DIF_7 Stoppable with OE7
RW
Free-run
Stoppable
0
Bit 6
DIF_6
DIF_6 Stoppable with OE6
RW
Free-run
Stoppable
0
Bit 5
DIF_5
DIF_5 Stoppable with OE5
RW
Free-run
Stoppable
0
Bit 4
DIF_4
DIF_4 Stoppable with OE4
RW
Free-run
Stoppable
0
Bit 3
DIF_3
DIF_3 Stoppable with OE3
RW
Free-run
Stoppable
0
Bit 2
DIF_2
DIF_2 Stoppable with OE2
RW
Free-run
Stoppable
0
Bit 1
DIF_1
DIF_1 Stoppable with OE1
RW
Free-run
Stoppable
0
Bit 0
DIF_0
DIF_0 Stoppable with OE0
RW
Free-run
Stoppable
0
SMBus Table: Reserved Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Reserved
30,29
20,21
16,17
12,13
8,9
Byte 3
20,21
16,17
12,13
8,9
Byte 2
42,41
38,37
34,33
-
Byte 1
42,41
38,37
34,33
30,29
See Bypass
Readback Table
See Bypass
Readback Table
-
Reserved
Byte 0
-
相關(guān)PDF資料
PDF描述
9DB833AGILF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB833AGLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB833AGILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB833AFILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB833AFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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