參數(shù)資料
型號: 9DB823BFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48
文件頁數(shù): 19/21頁
文件大?。?/td> 185K
代理商: 9DB823BFLF
IDT
Eight Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1444E - 05/09/11
9DB823B
Eight Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
7
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
VIL
3.3 V +/-5%
GND - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
1
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
uA
1
Operating Supply Current
IDD3.3OP
Full Active, CL = Full load;
200
mA
1
all diff pairs driven
60
mA
1
all differential pairs tri-stated
6
mA
1
FiPLL
PCIe Mode (Bypass/133/100= 1)
50
100.00
110
MHz
1
FiPLL
QPI Mode (Bypass/133/100= M)
67
133.33
140
MHz
1
FiBYPASS
Bypass Mode (Bypass/133/100= 0)
33
400
MHz
1
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs, except SRC_IN
1.5
5
pF
1
CINSRC_IN
SRC_IN differential clock inputs
1.5
2.7
pF
1,4
COUT
Output pin capacitance
6
pF
1
-3dB point in High BW Mode
2
3
4
MHz
1
-3dB point in Low BW Mode
0.7
1
1.4
MHz
1
PLL Jitter Peaking
tJPEAK
Peak Pass band Gain
1.5
2
dB
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1ms
1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
33
kHz
1
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1
3
cycles
1,3
Tdrive_DIF_Stop#
tDRVSTP
DIF output enable after
DIF_Stop# de-assertion
10
ns
1,3
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
300
us
1,3
Tfall
tF
Fall time of PD# and DIF_Stop#
5
ns
1
Trise
tR
Rise time of PD# and DIF_Stop#
5
ns
2
SMBus Voltage
VMAX
Maximum input voltage
5.5
V
1
Low-level Output Voltage
VOL
@ IPULLUP
0.4
V
1
Current sinking at VOL
IPULLUP
4mA
1
SCLK/SDATA
Clock/Data Rise Time
tRSMB
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
tFSMB
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
SMBus Operating Frequency
fMAXSMB
Maximum SMBus operating frequency
100
kHz
1,5
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
5The differential input clock must be running for the SMBus to be active
IDD3.3PD
3Time from deassertion until outputs are >200 mV
Input Low Current
Powerdown Current
PLL Bandwidth
BW
Input Frequency
Capacitance
4SRC_IN input
Symbol
Parameter
Min
Max
Units
VDDA/R
3.3V Core Supply Voltage
4.6
V
VDD
3.3V Logic Supply Voltage
4.6
V
VIL
Input Low Voltage
GND-0.5
V
VIH
Input High Voltage
VDD+0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protection
human body model
2000
V
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