參數(shù)資料
型號: 9DB803DGT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
文件頁數(shù): 3/21頁
文件大小: 249K
代理商: 9DB803DGT
IDTTM/ICSTM
Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803D
REV G 01/13/09
ICS9DB803D
Eight Output Differential Buffer for PCIe for Gen 2
11
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
Unit
Figure
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
inch
1
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
1
L3 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
1
Rs
33
ohm
1
Rt
49.9
ohm
1
Down Device Differential Routing
Dimension or Value
Unit
Figure
L4 length, Route as coupled microstrip 100 ohm differential trace.
2 min to 16 max
inch
1
L4 length, Route as coupled stripline 100 ohm differential trace.
1.8 min to 14.4 max
inch
1
Differential Routing to PCI Express Connector
Dimension or Value
Unit
Figure
L4 length, Route as coupled microstrip 100 ohm differential trace.
0.25 to 14 max
inch
2
L4 length, Route as coupled stripline 100 ohm differential trace.
0.225 min to 12.6 max
inch
2
Figure 1 Down device routing.
Rs
Rt
HSCL Output
Buffer
PCI Ex Board
Down Device
REF_CLK Input
L1
L2
L3’
L4
L1’
L2’
L3
L4’
Figure 1
Figure 2 PCI Express Connector Routing.
Rs
Rt
HSCL Output
Buffer
PCI Ex
Add In Board
REF_CLK Input
L1
L2
L3’
L4
L1’
L2’
L3
L4’
Figure 2
相關(guān)PDF資料
PDF描述
9DB823BFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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9DB833AGLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB833AGILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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