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參數(shù)資料
| 型號： | 9DB801CGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 129K |
| 代理商： | 9DB801CGLFT |
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz)
9DB801C
REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
4
Pin Description for OE_INV = 0
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
25
GND
POWER
Ground pin.
26
PD#
INPUT
Asynchronous active low input pin, with 120Kohm internal pull-
up resistor, used to power down the device. The internal clocks
are disabled and the VCO and the crystal are stopped.
27
SRC_STOP#
INPUT
Active low input to stop SRC outputs.
28
HIGH_BW#
INPUT
3.3V input for selecting PLL Band Width
0 = High, 1= Low
29
DIF_4#
OUTPUT
0.7V differential complement clock outputs
30
DIF_4
OUTPUT
0.7V differential true clock outputs
31
VDD
POWER
Power supply, nominal 3.3V
32
GND
POWER
Ground pin.
33
DIF_5#
OUTPUT
0.7V differential complement clock outputs
34
DIF_5
OUTPUT
0.7V differential true clock outputs
35
OE_5
INPUT
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
36
OE_6
INPUT
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
37
DIF_6#
OUTPUT
0.7V differential complement clock outputs
38
DIF_6
OUTPUT
0.7V differential true clock outputs
39
VDD
POWER
Power supply, nominal 3.3V
40
OE_INV
INPUT
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
41
DIF_7#
OUTPUT
0.7V differential complement clock outputs
42
DIF_7
OUTPUT
0.7V differential true clock outputs
43
OE_4
INPUT
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
44
OE_7
INPUT
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
45
LOCK
OUTPUT
3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
46
IREF
INPUT
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
47
GNDA
POWER
Ground pin for the PLL core.
48
VDDA
POWER
3.3V power for the PLL core.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DB803DFILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DGILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DFILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB803DFILF | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB803DFILFT | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB803DFLF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB803DFLFT | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB803DGILF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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