參數(shù)資料
型號: 9DB433AGILFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28
文件頁數(shù): 15/16頁
文件大?。?/td> 190K
代理商: 9DB433AGILFT
IDT
Four Output Differential Buffer for PCIe Gen 3
1658B - 05/09/11
9DB433
Four Output Differential Buffer for PCIe Gen 3
8
Common Recommendations for Differential Routing
Dimension or Value
Unit
Figure
L1 length, route as non-coupled 50ohm trace
0.5 max
inch
1
L2 length, route as non-coupled 50ohm trace
0.2 max
inch
1
L3 length, route as non-coupled 50ohm trace
0.2 max
inch
1
Rs
33
ohm
1
Rt
49.9
ohm
1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
inch
1
L4 length, route as coupled stripline 100ohm differential trace
1.8 min to 14.4 max
inch
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
inch
2
L4 length, route as coupled stripline 100ohm differential trace
0.225 min to 12.6 max
inch
2
Output Termination and Layout Information
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3
L3'
Rt
PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3
L3'
Rt
PCI Express
Add-in Board
REF_CLK Input
Figure 2: Differential Routing to PCI Express Controller
相關(guān)PDF資料
PDF描述
9DB433AFLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB633AFLIFT 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB633AGILF 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB633AFLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB633AGILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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