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參數(shù)資料
| 型號： | 9DB403DFILFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 194K |
| 代理商： | 9DB403DFILFT |
IDTTM/ICSTM
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
ICS9DB403D
REV N 05/09/11
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
12
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PD_Mode
PD# drive mode
RW
driven
Hi-Z
0
Bit 6
STOP_Mode
SRC_Stop# drive mode
RW
driven
Hi-Z
0
Bit 5
PD_Polarity
Select PD polarity
RW
Low
High
0
Bit 4
Reserved
RW
X
Bit 3
Reserved
RW
X
Bit 2
PLL_BW#
Select PLL BW
RW
High BW
Low BW
1
Bit 1
BYPASS#
BYPASS#/PLL
RW
fan-out
ZDB
1
Bit 0
SRC_DIV#
SRC Divide by 2 Select
RW
x/2
1x
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
RW
1
Bit 6
DIF_6
Output Enable
RW
Disable
Enable
1
Bit 5
DIF_5
Output Enable
RW
Disable
Enable
1
Bit 4
Reserved
RW
1
Bit 3
Reserved
RW
1
Bit 2
DIF_2
Output Enable
RW
Disable
Enable
1
Bit 1
DIF_1
Output Enable
RW
Disable
Enable
1
Bit 0
Reserved
RW
1
NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!
SMBus Table: OE Pin Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
RW
0
Bit 6
DIF_6
DIF_6 Stoppable with OE6
RW
Free-run
Stoppable
0
Bit 5
Reserved
RW
0
Bit 4
Reserved
RW
0
Bit 3
Reserved
RW
0
Bit 2
Reserved
RW
0
Bit 1
DIF_1
DIF_1 Stoppable with OE1
RW
Free-run
Stoppable
0
Bit 0
Reserved
RW
0
SMBus Table: Reserved Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Reserved
6,7
-
Byte 3
Reserved
-
Byte 0
-
6,7
19,20
-
9,10
-
Byte 2
22,23
Reserved
-
Byte 1
-
22,23
Reserved
-
Reserved
-
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DB403DFILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB403DGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB403DFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB403DFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB423BFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB403DFLF | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB403DFLFT | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB403DGILF | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB403DGILFT | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB403DGLF | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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