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參數(shù)資料
| 型號： | 9DB401CFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 160K |
| 代理商： | 9DB401CFLF |
IDT
Four Output Differential Buffer for PCI Express
9DB401C
REV H 01/27/11
9DB401C
Four Output Differential Buffer for PCI Express
5
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
4.6
V
VDD_In
3.3V Logic Supply Voltage
4.6
V
VIL
Input Low Voltage
GND-0.5
V
VIH
Input High Voltage
VDD+0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protection
human body model
2000
V
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
Input Low Voltage
VIL
3.3 V +/-5%
GND - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
uA
IIL1
VIN = 0 V; Inputs with no pull-
up resistors
-5
uA
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
IDD3.3PLL
175
200
mA
IDD3.3ByPass
160
175
mA
all diff pairs driven
40
mA
all differential pairs tri-stated
4
mA
Input Frequency
FiPLL
PLL Mode
50
200
MHz
Input Frequency
FiBypass
Bypass Mode (Revision
B/REV ID = 1H)
0
333.33
MHz
Input Frequency
FiBypass
Bypass Mode (Revision
C/REV ID = 2H)
0400
MHz
Pin Inductance
1
Lpin
7nH
1
CIN
Logic Inputs
1.5
4
pF
1
COUT
Output pin capacitance
4
pF
1
PLL Bandwidth when
PLL_BW=0
2.4
3
3.4
MHz
1
PLL Bandwidth when
PLL_BW=1
0.7
1
1.4
MHz
1
Clk Stabilization
1,2
TSTAB
From VDD Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
0.5
1
ms
1,2
Modulation Frequency
fMOD
Triangular Modulation
30
33
kHz
1
Tdrive_SRC_STOP#
DIF output enable after
SRC_Stop# de-assertion
10
15
ns
1,3
Tdrive_PD#
DIF output enable after
PD# de-assertion
300
us
1,3
Tfall
Fall time of PD# and
SRC_STOP#
5ns
1
Trise
Rise time of PD# and
SRC_STOP#
5ns
2
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
IDD3.3PD
3Time from deassertion until outputs are >200 mV
Input Capacitance
1
Input Low Current
Powerdown Current
PLL Bandwidth
BW
Operating Supply Current
Full Active, CL = Full load;
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB401CFLFT | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB401CGLF | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB401CGLFT | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB403DFILF | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB403DFILFT | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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