參數(shù)資料
型號(hào): 9DB233AFLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: 0.150 INCH, ROHS COMPLIANT, SSOP-20
文件頁(yè)數(shù): 8/14頁(yè)
文件大?。?/td> 160K
代理商: 9DB233AFLFT
IDT
Two Output Differential Buffer for PCIe Gen3
1667C—04/20/11
9DB233
Two Output Differential Buffer for PCIe Gen3
3
Datasheet
Pin Description
PIN # PIN NAME
PIN TYPE
DESCRIPTION
1PLL_BW
IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
2
SRC_IN
IN
0.7 V Differential SRC TRUE input
3
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
4v OE0#
IN
Activ e low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
5
VDD
PWR
Power supply , nominal 3.3V
6GND
PWR
Ground pin.
7
DIF_0
OUT
0.7V differential true clock output
8
DIF_0#
OUT
0.7V differential Complementary clock output
9
VDD
PWR
Power supply , nominal 3.3V
10
SMBDAT
I/O
Data pin of SMBUS c ircuitry, 5V tolerant
11
SMBCLK
IN
Clock pin of SMBUS c ircuitry, 5V tolerant
12
VDD
PWR
Power supply , nominal 3.3V
13
DIF_1#
OUT
0.7V differential Complementary clock output
14
DIF_1
OUT
0.7V differential true clock output
15
GND
PWR
Ground pin.
16
VDD
PWR
Power supply , nominal 3.3V
17
v OE1#
IN
Activ e low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18
IREF
OUT
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different v alues. See
data sheet.
19
GNDA
PWR
Ground pin for the PLL c ore.
20
VDDA
PWR
3.3V power for the PLL core.
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
Note:
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