參數(shù)資料
型號: 9DB202CK-01T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32
封裝: 5 X 5 MM, 0.95 MM HEIGHT, MO-220, VFQFN-32
文件頁數(shù): 14/17頁
文件大小: 356K
代理商: 9DB202CK-01T
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
6
ICS9DB202CK-01 REV. B FEBRUARY 18, 2009
ICS9DB202-01
PCI EXPRESS JITTER ATTENUATOR
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
FIGURE 1. POWER SUPPLY FILTERING
24
Ω
V
DDA
10
μF
.01
μF
3.3V
.01
μF
V
DD
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS9DB202-01
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD and VDDA should be
individually connected to the power supply plane through vias,
and 0.01F bypass capacitors should be used for each pin.
Fig-
ure 1 illustrates this for a generic V
DD pin and also shows that
V
DDA requires that an additional 24Ω resistor along with a 10F
bypass capacitor be connected to the V
DDA pin.
相關(guān)PDF資料
PDF描述
9DB206CFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB206CF 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB206CLT 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB206CL 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB206CFLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9DB206CF 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS JITTER ATTENUATOR 28SSOP - Rail/Tube
9DB206CFLF 功能描述:時鐘合成器/抖動清除器 2 HCSL Output PCIe Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9DB206CFLFT 功能描述:時鐘合成器/抖動清除器 2 HCSL Output PCIe Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9DB206CFT 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS JITTER ATTENUATOR 28SSOP - Tape and Reel
9DB206CL 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS JITTER ATTENUATOR 28TSSOP - Rail/Tube