參數(shù)資料
型號： 992215731411
廠商： NXP SEMICONDUCTORS
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, CPGA96
封裝： PGA-96
文件頁數(shù)： 13/16頁
文件大小： 224K
代理商： 992215731411
1999 November
6
Philips Semiconductors
Product specification
Full Frame CCD Image Sensor
FTF3020-M
Timing diagrams (for default operation)
VD: Frame pulse
CR: Charge Reset
BLC: Black Level Clamp
A1 to A4: Vertical image clocks
C1 to C3: Horizontal register clocks
SSC: Start-Stop C-clocks
SG: Summing gate
RG: Reset gate
1 Tp = 1 clock period
2 Duty cycle = 50% and phase shift of the C clocks is 120 degrees.
Figure 3 - Timing diagrams
AC CHARACTERISTICS
MIN.
TYPICAL
MAX.
UNIT
Horizontal frequency (1/Tp)
1
Vertical frequency
Charge Reset (CR) time
Rise and fall times:
image clocks (A)
register clocks (C)
2
summing gate (SG)
reset gate (RG)
10
3
18
50
193.7
20
5
36
100
1/6 Tp
MHz
kHz
s
ns
2047
2046
2048
Sensor Output
A2, A3, A4
VD
BLC
D
A1
BB
D
1
2
3
Integration Time
Ahigh
CR
SSC
EXT. SHUTTER
H
L
SSC
A1
A2
A3
A4
CR
AHigh
VD
BLC
C1
C2
C3
SG
RG
SSC
Tp = 1 / 18MHz = 55.56ns
Pixel output sequence: 7 dummy, 20 black, 4 timing, 3072 active, 4 timing, 20 black
Line Time: 3487 x Tp = 193.7s
Pixel Timing
Black
Dummy
*
* During AHigh = H the phiA high level is increased from 10V to 14V (This is necessary during readout only)
*
B
BBB
B
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Tp
360
Tp
230
Tp
66
Tp
138
Tp
20
Tp
138
Tp
112
Tp
204
Tp
138
Tp
360
Tp
396
Tp
30
3127 pixels
Tp / 6
Frame Timing
Line Timing
1Tp
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