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參數(shù)資料
| 型號(hào)： | 98ULPA877AHI-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | PLASTIC, MO-205, M0-225, VFBGA-52 |
| 文件頁(yè)數(shù)： | 11/14頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | 98ULPA877AHI-T |
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6
ICS98ULPA877A
1177F—12/10/09
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (
t
), after power-up. During
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK# may be left floating after they have been driven low for one
complete clock cycle.
Timing Requirements
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
1.8V+0.1V @ 25°C
95
410
MHz
Application Frequency
Range
freqApp
1.8V+0.1V @ 25°C
160
410
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
15
s
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| 98ULPA877AHILF-T | 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 98ULPA877AKI-T | 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 98ULPA877AKILF-T | 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 98ULPA877AH-T | 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 99.272.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 98ULPA877AHLF | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877AHLFT | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877AHT | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877AKILF | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877AKILFT | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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