- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25554 > 98ULPA877AH-T (INTEGRATED DEVICE TECHNOLOGY INC) 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 PDF資料下載
參數(shù)資料
| 型號： | 98ULPA877AH-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | PLASTIC, MO-205, M0-225, VFBGA-52 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 159K |
| 代理商： | 98ULPA877AH-T |
7
ICS98ULPA877A
1177F—12/10/09
Notes:
1.
Switching characteristics guaranteed for application frequency range.
2.
Static phase offset shifted by design.
Switching Characteristics
1
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
(MHz)
MIN
TYP
MAX
UNITS
Output enable time
ten
OE to any output
4.73
8
ns
Output disable time
tdis
OE to any output
5.82
8
ns
160 to 270
-40
40
ps
271 to 410
-30
30
ps
160 to 270
-60
60
ps
271 to 410
-50
50
ps
Input Clock
1
2.5
4
v/ns
Output Enable (OE), (OS)
0.5
v/ns
Output clock slew rate
SLr1(o)
1.5
2.5
3
v/ns
tjit(cc+)
040
ps
tjit(cc-)
0-40
ps
160 to 270
-50
50
ps
271 to 410
-20
20
ps
Static Phase Offset
tSPO
2
271 to 410
-50
0
50
ps
t jit (per) + t ()dyn + t skew(o)
∑(su)
80
ps
t()dyn + tskew(o)
∑
t (h)
60
ps
160 to 270
40
ps
271 to 410
30
ps
SSC modulation frequency
30.00
33
kHz
SSC clock input frequency
deviation
0.00
-0.50
%
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
MHz
160 to 410
Period jitter
tjit (per)
Input slew rate
SLr1(i)
160 to 410
Cycle-to-cycle period jitter
t()dyn
Half-period jitter
tjit(hper)
Output to Output Skew
tskew
Dynamic Phase Offset
相關PDF資料 |
PDF描述 |
|---|---|
| 99.272.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| 99.270.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| 99.265.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| 99.264.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| 99.263.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 98ULPA877AKILF | 功能描述:時鐘驅動器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877AKILFT | 功能描述:時鐘驅動器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877AKLF | 功能描述:時鐘驅動器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877AKLFT | 功能描述:時鐘驅動器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877FHLF | 制造商:Integrated Device Technology Inc 功能描述:MICRON P/N 521-500297 - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。