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參數(shù)資料
| 型號： | 97ULP877BKLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 封裝： | GREEN, PLASTIC, MLF-40 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 252K |
| 代理商： | 97ULP877BKLF |
10
ICS97ULP877B
0981B—03/15/05
Figure 9. Dynamic Phase Offset
Figure 10. Time delay between OE and Clock Output (Y, Y)
t
( )
t
( )
FBIN
CK
t
( )dyn
t
( )dyn
t
( )dyn
t
( )dyn
SSC OFF
SSC ON
SSC OFF
50% VDDQ
ten
tdis
OE
Y/ Y
Y
50% VDDQ
Y
50% VDDQ
50 % VDDQ
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| 97ULP877BKLF/W | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK DRVR SGL 95MHZ TO 410MHZ 40PIN VFQFPN - Tape and Reel |
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