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參數(shù)資料
| 型號(hào)： | 97U877AKLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| 封裝： | MLF-40 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 1125K |
| 代理商： | 97U877AKLF-T |
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5
ICS97U877AHLF/AKLF
Advance Information
0792—12/18/03
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3.
Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4.
Differential cross-point voltage is expected to track variations of VDDQ and is the
voltage at which the differential signal must be crossing.
Recommended Operating Condition (see note1)
TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDDQ, AVDD
1.7
1.8
1.9
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.35 x VDDQ
V
OE, OS
0.35 x VDDQ
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.65 x VDDQ
V
OE, OS
0.65 x VDDQ
V
DC input signal voltage
(note 2)
VIN
-0.3
VDDQ + 0.3
V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.3
VDDQ + 0.4
V
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.6
VDDQ + 0.4
V
Output differential cross-
voltage (note 4)
VOX
VDDQ/2 - 0.10
VDDQ/2 + 0.10
V
Input differential cross-
voltage (note 4)
VIX
VDDQ/2 - 0.15 VDD/2 VDDQ2 + 0.15
V
High level output current
IOH
-9
mA
Low level output current
IOL
9mA
Operating free-air
temperature
TA
070
°C
Differential input signal
voltage (note 3)
VID
Low level input voltage
VIL
High level input voltage
VIH
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