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參數(shù)資料
| 型號(hào)： | 97U877AH |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | PLASTIC, VFBGA-52 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 215K |
| 代理商： | 97U877AH |
6
ICS97U877
0792A—04/15/04
Notes:
1.
Switching characteristics guaranteed for application frequency range.
2.
Static phase offset shifted by design.
Timing Requirements
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
1.8V+0.1V @ 25°C
95
370
MHz
Application Frequency Range
freqApp
1.8V+0.1V @ 25°C
160
350
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
15
s
Switching Characteristics
1
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Output enable time
ten
OE to any output
4.73
8
ns
Output disable time
tdis
OE to any output
5.82
8
ns
Period jitter
tjit (per)
-30
30
ps
Half-period jitter
tjit(hper)
-60
60
ps
Input Clock
1
2.5
4
v/ns
Output Enable (OE), (OS)
0.5
v/ns
Output clock slew rate
SLr1(o)
1.5
2.5
3
v/ns
tjit(cc+)
040
ps
tjit(cc-)
0
-40
ps
Dynamic Phase Offset
t( )dyn
-20
20
ps
Static Phase Offset
tSPO
2
-50
0
50
ps
Output to Output Skew
tskew
40
ps
SSC modulation frequency
30.00
33
kHz
SSC clock input frequency
deviation
0.00
-0.50
%
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
MHz
Cycle-to-cycle period jitter
Input slew rate
SLr1(i)
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| 97U877AKLF | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 1.8V DDR-II PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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