參數(shù)資料
型號(hào): 97SD3240RPQK
廠商: MAXWELL TECHNOLOGIES
元件分類(lèi): DRAM
英文描述: 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks
中文描述: 32M X 40 SYNCHRONOUS DRAM, 6 ns, QFP132
封裝: STACK, QFP-132
文件頁(yè)數(shù): 24/39頁(yè)
文件大?。?/td> 759K
代理商: 97SD3240RPQK
97SD3240
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All data sheets are subject to change without notice
2006 Maxwell Technologies
All rights reserved.
1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM
05.10.06 Rev 4
2. Same Bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It
is necessary to separate the two commands with a bank active command.
Read command to Precharge command Interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the
minimum interval between the two commands is one clock. However, since the output buffer than becomes
High-Z after the clock defined by I
HZP , there is a case of interruption to burst read data. Output will be
interrupted if the precharge command is input during burst read. To read all data by burst read, the clocks
defined by I
EP must be assured as an interval from the final data output to precharge command execution.
READ to PRECHARGE command Interval (same bank: To output all data)
CAS Latency = 2, Burst Length = 4
CAS Latency = 3, Burst Length = 4
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