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參數(shù)資料
| 型號： | 97SD3240RPQE |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 中文描述： | 32M X 40 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 封裝： | STACK, QFP-132 |
| 文件頁數(shù)： | 39/39頁 |
| 文件大?。?/td> | 759K |
| 代理商： | 97SD3240RPQE |
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97SD3240
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All data sheets are subject to change without notice
2006 Maxwell Technologies
All rights reserved.
1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM
05.10.06 Rev 4
Column address strobe and write command (WRIT): This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY9) and the bank select address (BA0/BA1)
become the burst write start address. When the single write mode is selected, data is only written to the
location specified by the column address (AY0 to AY9) and bank select address(BA0/BA1).
Write with auto-precharge (WRIT A): This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4, or 8, or after a single write operation.
Row address strobe and bank activate ( ACTV): This command activates the bank that is selected by
BA0/BA1 (BS) and determines the row address (AX0 to AX12). When BA0 and BA1 are Low, bank 0 is
activated. When BA0 is Low, and BA1 is High, bank 1 is activated. When BA0 is High and BA1 is Low, bank
2 is activated. When BA0 and BA1 are High, bank 3 is activated.
Precharge select bank (PRE): This command starts precharge operation for the bank selected by BA0/
BA1. If BA0 and BA1 are Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0
is High and BA1 is Low, bank 2 is selected. If BA0 and BA1 are High, bank 3 is selected.
Precharge all banks (PALL): This command starts a precharge operation for all banks.
Refresh (REF/SELF): This command starts the refresh operation. There are two types of refresh
operations; one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set (MRS): The SDRAM has a mode register that defines how it operates. The mode register
is specified by the address pins (A0 to A12, BA0 andBA1) at the mode register set cycle. For details, refer to
the mode register configuration. After power on, the contents of the mode register are undefined, execute
the mode register set command to set up the mode register.
相關PDF資料 |
PDF描述 |
|---|---|
| 97SD3240RPQH | 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240RPQI | 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240RPQK | 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240 | 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3248RPQE | 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 97SD3240RPQH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240RPQI | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240RPQK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3248 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248_06 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
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