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參數(shù)資料
| 型號： | 97SD3232RPMI |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | 1 Gb SDRAM 8-Meg X 32 Bit X 4-Banks |
| 中文描述： | 32M X 32 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 封裝： | STACK, QFP-132 |
| 文件頁數(shù)： | 6/39頁 |
| 文件大?。?/td> | 764K |
| 代理商： | 97SD3232RPMI |
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97SD3232
M
em
o
ry
14
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM
01.11.05 Rev 2
From PRECHARGE state, command operation
To [DESL], [NOP]: When these commands are executed, the SDRAM enters the IDLE state after t
RP has
elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [PRE], or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The synchronous DRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of t
RCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t
RCD is required.)
Write with auto-
precharge
H
x
DESL
Continue burst to end and pre-
charge
L
H
x
NOP
Continue burst to end and pre-
charge
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL1
L
H
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL1
L
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank4
L
H
L
BA, A10
PRE, PALL
ILLEGAL1
L
H
x
REF, SELF
ILLEGAL
L
MODE
MRS
ILLEGAL
Refresh ( auto-
refresh)
H
x
DESL
Enter IDLE after t
RC
L
H
x
NOP
Enter IDLE after t
RC
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL3
L
H
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL3
L
H
BA, RA
ACTV
ILLEGAL3
L
H
L
BA, A10
PRE, PALL
ILLEGAL3
L
H
x
REF, SELF
ILLEGAL
L
MODE
MRS
ILLEGAL
1. Illegal for same bank, except for another bank
2. NOP for same bank, except for another bank
3. Illegal for all banks
4. If t
RRD is not satisfied, this operation is illegal
5. An interval of t
DPL is required between the final valid data input and the precharge command
CURRENT STATE
CS
RAS
CAS
WE
ADDRESS
COMMAND
OPERATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 97SD3232RPMK | 1 Gb SDRAM 8-Meg X 32 Bit X 4-Banks |
| 97SD3232 | 1 Gb SDRAM 8-Meg X 32 Bit X 4-Banks |
| 97SD3240RPQE | 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240RPQH | 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240RPQI | 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 97SD3232RPMK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1 Gb SDRAM 8-Meg X 32 Bit X 4-Banks |
| 97SD3240 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240_06 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240RPQE | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
| 97SD3240RPQH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks |
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