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參數(shù)資料
| 型號： | 951601AFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 66.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 168K |
| 代理商： | 951601AFLFT |
4
ICS951601
Preliminary Product Preview
0663C—10/04/05
Byte 0: Functionality and frequency select register (Default = 0)
Serial Configuration Command Bitmap
Bit2 Bit7
Bit6
Bit5
Bit4
66MHZ 33MHz
FEATURES
FS4 FS3
FS2
FS1
FS0
0
0000
66
33
-0.25 % down spread
0
0001
66
33
-0.5 % down spread
0
0010
66
33
-1.0 % down spread
0
0011
66
33
-1.5 % down spread
0
0100
66
33
+ 0.25 % center spread
0
0101
66
33
+0.5 % center spread
0
0110
66
33
+ 1.0 % center spread
0
0111
66.6
33.3
+1.5 % center spread
0
1000
67.32
33.66
2% over-clocking
0
1001
68.64
34.32
4% over-clocking
0
1010
69.96
34.98
6% over-clocking
0
1011
72.6
36.3
10% over-clocking
0
1100
65.27
32.63
2% under- clocking
0
1101
63.96
31.97
2% under- clocking
0
1110
62.6
31.3
2% under- clocking
0
1111
60
30
2% under- clocking
1
0000
66.6
33.3
-1.4 % down spread
1
0001
66.6
33.3
-1.6 % down spread
1
0010
66.6
33.3
-1.8 % down spread
1
0011
66.6
33.3
-2.0 % down spread
1
0100
66.6
33.3
+ 1.4 % center spread
1
0101
66.6
33.3
+ 1.6 % center spread
1
0110
66.6
33.3
+ 1.8 % center spread
1
0111
66.6
33.3
+ 2.0 % center spread
Bit1
0-Normal
1-Spread spectrum Enabled
0
Bit0
0-Running 1-Tristate all outputs
0
Bit
PWD
00000
Bit
2,7:4
Bit3
0
0-Frequency and Spread is seleced by hardware select. Latched input
1-Frequency is seleced by Bit2, 7:4
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