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參數(shù)資料
| 型號： | 951601AFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 66.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 168K |
| 代理商： | 951601AFLF |
Integrated
Circuit
Systems, Inc.
ICS951601
Preliminary Product Preview
0663C—10/04/05
Block Diagram
General Purpose Frequency Timing Generator
Recommended Application:
General Purpose Clock Generator
Output Features:
17 - PCI clocks selectable,
either 33.33MHz or 66.6MHz @ 3.3V
1 - 48MHz @ 3.3V
1 - REF @ 3.3V, 14.318MHz.
Features:
Programable Spread spectrum precentage for EMI
control
Uses external 14.318MHz crystal
Select pins for frequency select
PLL2
PLL1
Spread
Spectrum
48MHz
PCI1A (7:0)
PCI2A (2:0)
PCI1B (2:0)
PCI2B (2:0)
8
3
X1
X2
XTAL
OSC
PCI
DIVDER
PCI
DIVDER
PCI
DIVDER
PCI
DIVDER
SDATA
SCLK
SELA (2:1)
SELB (2:1)
SPREAD
Control
Logic
Config.
Reg.
REF0
Power Groups:
VDDA = Analog Power
GNDA = Analog Ground
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.
Key Specifications:
PCI – PCI output skew within same bank @
33MHz: <170ps
PCI – PCI output skew within same bank@ 66MHz:
<340ps
Cycle to Cycle Jitter PCI @ 33MHz: <200ps
Cycle to Cycle Jitter PCI @ 66MHz: <200ps
Cycle to Cycle Jitter 48MHz: <350ps
Cycle to Cycle Jitter REF: <500ps
Slew Rate: 1.5 - 4 V/ns. (PCI spec.)
Pin Configuration
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
REF0
VDD
X1
X2
GND
SDATA
SCLK
GNDA
VDDA
SEL1A
PCI1A_0
PCI1A_1
VDD33
GND
PCI1A_2
PCI1A_3
GND
VDD33
PCI1A_4
PCI1A_5
VDD33
GND
PCI1A_6
PCI1A_7
48MHz
GND
VDD48
SPREAD
VDDA
GNDA
SEL2B
PCI2B_2
PCI2B_1
GND
VDD66
PCI2B_0
SEL2A
PCI2A_2
PCI2A_1
VDD2A
GND
PCI2A_0
SEL1B
PCI1B_2
PCI1B_1
GND
VDD1B
PCI1B_0
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