參數(shù)資料
型號(hào)： 951411BGLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
文件頁(yè)數(shù)： 15/21頁(yè)
文件大小： 225K
代理商： 951411BGLF
3
Integrated
Circuit
Systems, Inc.
ICS951411
0891E—03/07/05
Pin Description (Continued)
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
29
ATIGCLKC0
OUT Complementary clock of differential SRC clock pair.
30
ATIGCLKT0
OUT True clock of differential SRC clock pair.
31
GNDATI
PWR Ground for ATI Gclocks, nominal 3.3V
32
VDDATI
PWR Power supply ATI Gclocks, nominal 3.3V
33
SRCCLKC0
OUT Complement clock of differential SRC clock pair.
34
SRCCLKT0
OUT True clock of differential SRC clock pair.
35
VDDSRC
PWR Supply for SRC clocks, 3.3V nominal
36
GNDSRC
PWR Ground pin for the SRC outputs
37
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
38
GNDA
PWR Ground pin for the PLL core.
39
VDDA
PWR 3.3V power for the PLL core.
40
CPUCLKC2_ITP
OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
41
CPUCLKT2_ITP
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
42
CPUCLKC1
OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
43
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
44
GNDCPU
PWR Ground pin for the CPU outputs
45
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
46
CPUCLKC0
OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
47
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
48
*CPU_STOP#
IN
Stops all CPUCLK, except those set to be free running clocks
49
GNDPCI
PWR Ground pin for the PCI outputs
50
**CK410#/PCICLK0
I/O
FS Table select latch input pin / 3.3V PCI clock output.
0 = CK410 FS Table, 1 = CK409 FS Table
51
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
52
**TEST_SEL/REF2
I/O
TEST_SEL: latched input to select TEST MODE / 14.318 MHz reference clock.
1 = All outputs are CK410 REF/N test mode
0 = All outputs behave normally.
53
**FS_B/REF1
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
54
**FS_A/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
55
GND
PWR Ground pin.
56
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
951411BGLFT 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Generator Dual 56-Pin TSSOP T/R
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