參數(shù)資料
型號: 951402AFLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 210 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: GREEN, MO-118, SSOP-48
文件頁數(shù): 24/25頁
文件大?。?/td> 320K
代理商: 951402AFLFT
8
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2C Table: Output Control Register
Byte 6
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
CPU_STOP#
CPU Stop Status
RW
1
Bit 6
-
PD#
PD# Status
RW
See Table 1:
Truth Table on page 3
1
Bit 5
-
PCI_F0
Free-run Control
RW
Free
Not free
0
Bit 4
-
PCI_F1
Free-run Control
RW
Free
Not free
0
Bit 3
-
CPUT/C_0
Free-run Control
RW
Free
Not free
1
Bit 2
-
CPUT/C_1
Free-run Control
RW
Free
Not free
1
Bit 1
40,39
CPUT/C_0
Output Control
RW
Disable
Enable
1
Bit 0
44,43
CPUT/C_1
Output Control
RW
Disable
Enable
1
I
2C Table: Output Control Register
Byte 7
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
15
PCICLK_F1
Output Control
RW
Disable
Enable
1
Bit 6
14
PCICLK_F0
Output Control
RW
Disable
Enable
1
Bit 5
23
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 4
22
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 3
21
PCICLK3
Output Control
RW
Disable
Enable
1
Bit 2
20
PCICLK2
Output Control
RW
Disable
Enable
1
Bit 1
17
PCICLK1
Output Control
RW
Disable
Enable
1
Bit 0
16
PCICLK0
Output Control
RW
Disable
Enable
1
I
2C Table: Byte Count Register
Byte 8
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
BC7
RW
-
0
Bit 6
-
BC6
RW
-
0
Bit 5
-
BC5
RW
-
0
Bit 4
-
BC4
RW
-
0
Bit 3
-
BC3
RW
-
1
Bit 2
-
BC2
RW
-
1
Bit 1
-
BC1
RW
-
1
Bit 0
-
BC0
Writing to this
register will configure
how many bytes will
be read back, default
is 0F = 15 bytes.
RW
-
1
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