參數(shù)資料
型號(hào)： 950405AFLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 300 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： 0.300 INCH, GREEN, MO-118, SSOP-48
文件頁(yè)數(shù)： 11/18頁(yè)
文件大小： 219K
代理商： 950405AFLFT
2
ICS950405
0802F—04/22/05
Pin Descriptions
PIN # PIN NAME
PIN
TYPE
DESCRIPTION
1
*FS0/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
2
VDDHTT
PWR
Supply for HTT clocks, nominal 3.3V.
3
X1
IN
Crystal input, Nominally 14.318MHz.
4
X2
OUT
Crystal output, Nominally 14.318MHz
5
GND
PWR
Ground pin.
6
*ModeA/HTTCLK0
I/O
Mode selection latch input pin / Hyper Transport output.
7
*ModeB/PCICLK8/HTTCLK1
I/O
Mode selection latch input pin / PCI clock output / Hyper Transport output.
8
PCICLK9/HTTCLK2
OUT
PCI clock output / Hyper Transport output.
9
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
10
GND
PWR
Ground pin.
11
PCICLK11/HTTCLK3
I/O
PCI clock output / Hyper Transport output.
12
PCICLK10
OUT
PCI clock output.
13
PCICLK0
OUT
PCI clock output.
14
PCICLK1
OUT
PCI clock output.
15
GND
PWR
Ground pin.
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
PCICLK2
OUT
PCI clock output.
18
PCICLK3
OUT
PCI clock output.
19
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
20
GND
PWR
Ground pin.
21
2XPCICLK4
OUT
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
22
2XPCICLK5
OUT
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
23
2XPCICLK6
OUT
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
24
2XPCICLK7
OUT
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
25
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
26
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
27
GND
PWR
Ground pin.
28
24_48MHz/Sel24_48#*
I/O
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
29
AVDD48
PWR
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
30
GND
PWR
Ground pin.
31
48MHz/FS3**
I/O
Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin
32
PD#*
IN
Asynchronous active low input pin used to power down the device into a low power state.
The internal clocks are disabled and the VCO and the crystal are stopped.
33
GND
PWR
Ground pin.
34
GND
PWR
Ground pin.
35
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
36
CPUCLK8C1
OUT
Complimentary clock of differential 3.3V push-pull K8 pair.
37
CPUCLK8T1
OUT
True clock of differential 3.3V push-pull K8 pair.
38
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
39
GND
PWR
Ground pin.
40
CPUCLK8C0
OUT
Complimentary clock of differential 3.3V push-pull K8 pair.
41
CPUCLK8T0
OUT
True clock of differential 3.3V push-pull K8 pair.
42
GND
PWR
Ground pin.
43
VDDA
PWR
3.3V power for the PLL core.
44
Reset#
OUT
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
45
REF2/FS2*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
46
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
47
GND
PWR
Ground pin.
48
REF1/FS1*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
相關(guān)PDF資料
PDF描述
950405AFLF 300 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
950515 20 A, MODULAR TERMINAL BLOCK, 1 ROW, 1 DECK
950513 20 A, MODULAR TERMINAL BLOCK, 1 ROW, 1 DECK
950511 20 A, MODULAR TERMINAL BLOCK, 1 ROW, 1 DECK
950510 20 A, MODULAR TERMINAL BLOCK, 1 ROW, 1 DECK
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