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參數(shù)資料
| 型號： | 950405AFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 300 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 219K |
| 代理商： | 950405AFLF |
8
ICS950405
0802F—04/22/05
I
2C Table: Skew Control Register
Bit 7
PCI/HTTSkw3
RW
0000:0
0100:150 1000:300 1100:450
1
Bit 6
PCI/HTTSkw2
RW
0001:N/A 0101:N/A 1001:N/A 1101:600
1
Bit 5
PCI/HTTSkw1
RW
0010:N/A 0110:N/A 1010:N/A 1110:750
0
Bit 4
PCI/HTTSkw0
RW
0011:N/A 0111:N/A 1011:N/A 1111:900
0
Bit 3
PCISkw3
RW
0000:0
0100:150 1000:300 1100:450
1
Bit 2
PCISkw2
0001:N/A 0101:N/A 1001:N/A 1101:600
1
Bit 1
PCISkw1
RW
0010:N/A 0110:N/A 1010:N/A 1110:750
0
Bit 0
PCISkw0
RW
0011:N/A 0111:N/A 1011:N/A 1111:900
0
I
2C Table: WD Time Control & Async Frequency Selection Register
Bit 7
ASEL
Async Frequency
Select
RW
0
Bit 6
AEN
AGP/PCI/ Freq Source
Select
RW
1
Bit 5
Reserved
RW
X
Bit 4
Reserved
RW
X
Bit 3
WDTCtrl
Watch Dog Time base
Control
RW
0
Bit 2
WD2
WD Timer Bit 2
RW
1
Bit 1
WD1
WD Timer Bit 1
RW
1
Bit 0
WD0
WD Timer Bit 0
RW
1
I
2C Table: VCO Control Select Bit & WD Timer Control Register
Bit 7
M/NEN
M/N Programming
Enable
RW
0
Bit 6
WDEN
Watchdog Enable
RW
0
Bit 5
WDStatus
WD Alarm Status
R
0
Bit 4
WD SF4
RW
0
Bit 3
WD SF3
RW
0
Bit 2
WD SF2
RW
0
Bit 1
WD SF1
RW
0
Bit 0
WD SF0
RW
0
I
2C Table: VCO Frequency Control Register
Bit 7
N Div8
N Divider Prog bit 8
RW
X
Bit 6
N Div9
N Divider Prog bit 9
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
CPU-PCI/HTT 7 Step
Skew Control (ps)
CPU-PCI 7 Step Skew
Control (ps)
M Divider Programming
bits (5:0)
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
The decimal representation of N Divider in
Byte 11 and 12
Type
0
1
-
PWD
Byte 11
Pin #
Name
Control Function
-
Normal
Alarm
-
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
-
Disable
Enable
-
Disable
Enable
1PWD
Byte 10
Pin #
Name
Control Function
Type
0
-
These bits represent X*290ms (or 1.16S)
the watchdog timer waits before it goes to
alarm mode. Default is 7 X 290ms = 2s.
-
--
-
290ms Base
1160ms Base
-
66MHz
75.4MHz
FIX PLL
CPU PLL
--
Type
0
1
PWD
Byte 9
Pin #
Name
Control Function
-
Type
0
1
PWD
Byte 8
Pin #
Name
Control Function
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 950405AFLFT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9504-060-U500 | 制造商:Belden Inc 功能描述: |
| 950406-5002-AR | 功能描述:集管和線殼 6P BDMNT SKT 2R STRT PTH 10U AU RoHS:否 產(chǎn)品種類:1.0MM Rectangular Connectors 產(chǎn)品類型:Headers - Pin Strip 系列:DF50 觸點類型:Pin (Male) 節(jié)距:1 mm 位置/觸點數(shù)量:16 排數(shù):1 安裝風(fēng)格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點材料:Brass 觸點電鍍:Gold 制造商:Hirose Connector |
| 950406-6102-AR | 功能描述:集管和線殼 6P BD MNT SKT 2R STRT PTH 10U AU RoHS:否 產(chǎn)品種類:1.0MM Rectangular Connectors 產(chǎn)品類型:Headers - Pin Strip 系列:DF50 觸點類型:Pin (Male) 節(jié)距:1 mm 位置/觸點數(shù)量:16 排數(shù):1 安裝風(fēng)格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點材料:Brass 觸點電鍍:Gold 制造商:Hirose Connector |
| 950406-7203-AR | 功能描述:集管和線殼 6P BDMNT SKT 2R STRT PTH 10U AU RoHS:否 產(chǎn)品種類:1.0MM Rectangular Connectors 產(chǎn)品類型:Headers - Pin Strip 系列:DF50 觸點類型:Pin (Male) 節(jié)距:1 mm 位置/觸點數(shù)量:16 排數(shù):1 安裝風(fēng)格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點材料:Brass 觸點電鍍:Gold 制造商:Hirose Connector |
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