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參數(shù)資料
| 型號： | 9412AVK |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 2 MM HEIGHT, PLASTIC, MS-022, MQFP-80 |
| 文件頁數(shù)： | 51/126頁 |
| 文件大?。?/td> | 1673K |
| 代理商： | 9412AVK |
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DATA SHEET
30
Aug. 16, 2004; 6251-552-1DS
Micronas
2.5.6. Digital 656 Input
The IC decodes a digital 8 bit@27 MHz data stream
according to ITU.BT656 standard. The configuration is
set by EN_656. and DPOUT656.
Four input modes are supported:
To adjust the input to sources, which deviate from the
standard, the field information may be inverted
(F_POL) and the chrominance format can be chosen
between unsigned and 2’s complement format (CFOR-
MAT). The polarity of H an V can be inverted by
H_POL and V_POL respectively. Dependent on ver-
sion, the digital input must be selected by ITUPRTSEL
(pins i656i or 656io).
2.5.7. Digital 656 Output
Dependent on version (single- or double-scan), the
output data format corresponds to CCIR 656 (8-bit bus
at a data rate of 27 MHz) or has double-scan format
(8-bit bus at a data rate of 54 MHz). There all frequen-
cies and data-rates are doubled compared to standard
CCIR656 specification. Double scan format is intended
to be used with a suited backend device, e.g.
DDP3315C. Timing reference codes (SAV, EAV) are
inserted according to the specification. The output can
be enabled by DPOUT656. The output should be set
to 720 pixels per line (APPLOP) and the display clock
should be set to 27/54 MHz (refer to Chapter 2.6.).
The chrominance information can be inverted by
CHRMSIG656. HOUT and VOUT pins may be used in
parallel.
2.6. Clock Concept
A single 20.25 MHz crystal at fundamental mode is
used as clock reference. All other clocks are derived
from this source. The CVBS front-end works with
20.25 MHz, the RGB front-end works with 40.5 MHz,
the oversampling DACs use CLKB72 and the memory
and all parts behind the memory are clocked with
CLKB36. The frequency of CLKB36 and CLKB72 is
adjustable and depends on application. With analog
output, CLKB72 is usually 72 MHz and with digital out-
put, CLKB72 is usually 54 MHz. CLKB72 is always
twice of CLKB36.
Three different clock concepts are supported. The dif-
ference is the behavior in clocking the memory output.
The front-end part of the VSP 94x2A uses a freeruning
but crystal-stable clock (CLKF). After deskewing, an
orthogonal picture is written into the memory. The read
out is done using the (CLKB) clock.
The horizontal sync-signal output (HOUT) is derived
from a counter running with CLKB. The VOUT is
directly derived from the input vertical signal, which is
generated by the sync-separation block. This ‘H-fre-
erunning-V-locked mode’ is only possible together with
a DC coupled deflection controller.
In ‘H-and-V-locked mode’ CLKB is line-locked to the
incoming signal. The freerunning YUV picture data
and the internal H signal are converted to the line-
locked domain. Now HOUT and the sync signal in the
1fH domain are directly coupled.
In case of ‘H-and-V-freerunning mode’ the HOUT and
VOUT signals are derived from counters running with
CLKB. There is no connection to the incoming signal.
This mode can be used for stable pictures when no
signal is applied (e.g. channel search with OSD inser-
tion).
Table 2–15: 656 input / output selection
EN_656
DPOUT656
656 Operation
0
Input disabled/
output disabled
0
1
Input disabled/
output enabled
1
0
Input enabled/
output disabled
1
Input enabled/
output disabled
(9412A only)
Table 2–16: 656 modes
IMODE
656 Operation
00
Full ITU mode (automatic)
Information about active picture is taken
from data-stream
01
Full ITU mode (manual)
Information about active picture is taken
from APPLIPI, NAPPLIPI, ALPFIPI,
NALPFIPI
10
ITU656 only data, H/V-sync according
PAL/NTSC
11
ITU656 only data, H/V-sync according
ITU656
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