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參數(shù)資料
| 型號： | 93V855AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, GREEN, MO-153, TSSOP-28 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 93K |
| 代理商： | 93V855AGLF |
2
ICS93V855I
0783C—06/01/04
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
GND
PWR
Ground pin.
2
DDRC0
OUT
"Complimentary" Clock of differential pair output.
3
DDRT0
OUT
"True" Clock of differential pair output.
4
VDD2.5
PWR
Power supply, nominal 2.5V
5
CLK_INT
IN
"True" reference clock input.
6
CLK_INC
IN
"Complimentary" reference clock input.
7
AVDD2.5
PWR
2.5V Analog Power pin for Core PLL
8
AGND
PWR
Analog Ground pin for Core PLL
9
GND
PWR
Ground pin.
10
DDRC1
OUT
"Complimentary" Clock of differential pair output.
11
DDRT1
OUT
"True" Clock of differential pair output.
12
VDD2.5
PWR
Power supply, nominal 2.5V
13
DDRT2
OUT
"True" Clock of differential pair output.
14
DDRC2
OUT
"Complimentary" Clock of differential pair output.
15
GND
PWR
Ground pin.
16
DDRC3
OUT
"Complimentary" Clock of differential pair output.
17
DDRT3
OUT
"True" Clock of differential pair output.
18
VDD2.5
PWR
Power supply, nominal 2.5V
19
GND
PWR
Ground pin.
20
FB_INC
IN
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase error.
21
FB_INT
IN
True single-ended feedback input, provides feedback signal to internal
PLL for synchronization with CLK_INT to eliminate phase error.
22
VDD2.5
PWR
Power supply, nominal 2.5V
23
FB_OUTT
OUT
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs, This output must
be connect to FB_INT.
24
FB_OUTC
OUT
Complement single-ended feedback output, dedicated external feedback.
It switches at the same frequency as other DDR outputs, This output must
be connect to FB_INC.
25
GND
PWR
Ground pin.
26
VDD2.5
PWR
Power supply, nominal 2.5V
27
DDRT4
OUT
"True" Clock of differential pair output.
28
DDRC4
OUT
"Complimentary" Clock of differential pair output.
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