參數(shù)資料
型號: 93LC86BT-I/P
元件分類: PROM
英文描述: 128 X 8 MICROWIRE BUS SERIAL EEPROM, PDIP8
封裝: 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-8
文件頁數(shù): 7/38頁
文件大?。?/td> 700K
代理商: 93LC86BT-I/P
2007 Microchip Technology Inc.
DS21929D-page 15
93XX46X/56X/66X/76X/86X
3.8
WRITE
The WRITE instruction is followed by 8 bits (If ORG is
low or A-version devices) or 16 bits (If ORG pin is high
or B-version devices) of data which are written into the
specified address. For 93AAXX and 93LCXX devices,
after the last data bit is clocked into DI, the falling edge
of CS initiates the self-timed auto-erase and program-
ming cycle. For 93CXX devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit.
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
FIGURE 3-8:
WRITE TIMING FOR 93AAXX AND 93LCXX DEVICES
FIGURE 3-9:
WRITE TIMING FOR 93CXX DEVICES
Note:
For devices with PE functionality such as
the 93XX76C or 93XX86C, the write
sequence requires a logic high signal on
the PE pin prior to the rising edge of clock
on the last data bit.
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
1
0
1
An
A0
Dx
D0
Busy
Ready
High-Z
Twc
TCSL
TCZ
TSV
CS
CLK
DI
DO
1
0
1
An
A0
Dx
D0
Busy
Ready
High-Z
Twc
TCSL
TCZ
TSV
相關PDF資料
PDF描述
93AA76B-I/P 128 X 8 MICROWIRE BUS SERIAL EEPROM, PDIP8
93LC76B-I/MS 512 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
93C66BT-I/P 128 X 8 MICROWIRE BUS SERIAL EEPROM, PDIP8
93LC66CT-I/OT 256 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO6
93C76A-I/MC 512 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
相關代理商/技術參數(shù)
參數(shù)描述
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