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參數(shù)資料
| 型號(hào)： | 93LC86-ISN |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 16-Bit Buffers/Drivers With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 8K/16K 2.5V的微型導(dǎo)線串行EEPROM |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 86K |
| 代理商： | 93LC86-ISN |
1996 Microchip Technology Inc.
Preliminary
DS21131C-page 3
93LC76/86
TABLE 1-3:
AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
V
CC
= +2.5V to +6.0V
Commercial (C): Tamb = 0C to +70C
Industrial (I): Tamb = -40C to +85C
Parameter
Symbol
Clock frequency
F
CLK
Min.
—
Max.
3
2
—
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
cycles
Conditions
4.5V
≤
2.5V
≤
4.5V
≤
2.5V
≤
4.5V
≥
2.5V
≤
4.5V
≤
2.5V
≤
V
CC
<
4.5V, Relative to CLK
V
V
V
V
V
V
V
CC
≤
6.0V, Relative to CLK
CC
CC
≤
<
≤
<
≤
<
6.0V
4.5V
6.0V
4.5V
6.0V
4.5V
Clock high time
T
CKH
200
300
100
200
50
100
0
250
50
100
50
100
—
CC
CC
Clock low time
T
CKL
—
CC
CC
Chip select setup time
T
CSS
—
Chip select hold time
Chip select low time
Data input setup time
T
CSH
T
CSL
T
DIS
—
—
—
Relative to CLK
4.5V
≤
V
CC
≤
6.0V, Relative to CLK
2.5V
≤
V
CC
<4.5V, Relative to CLK
4.5V
≤
V
CC
≤
6.0V, Relative to CLK
2.5V
≤
V
CC
<
4.5V, Relative to CLK
4.5V
≤
V
CC
≤
6.0V, C
L
= 100 pF
2.5V
≤
V
CC
< 4.5V, C
L
= 100 pF
4.5V
≤
V
CC
≤
6.0V
2.5V
≤
V
CC
< 4.5V (Note 1)
4.5V
≥
V
CC
≤
6.0V, C
L
= 100 pF
2.5V
≤
V
CC
<4.5V, C
L
= 100 pF
ERASE/WRITE mode
ERAL mode
WRAL mode
25
°
C, Vcc = 5.0V, Block Mode
(Note 2)
Data input hold time
T
DIH
—
Data output delay time
T
PD
100
250
100
500
200
300
5
15
30
—
Data output disable time
T
CZ
—
Status valid time
T
SV
—
Program cycle time
T
WC
T
EC
T
WL
—
—
—
—
10M
Endurance
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be found on our BBS or website.
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