參數(shù)資料
型號: 93LC56B
廠商: Microchip Technology Inc.
英文描述: 2K 2.5V Microwire Serial EEPROM(2K位,2.5V,具上掉電數(shù)據(jù)保護(hù)電路,Microwire接口EEPROM)
中文描述: 2K Microwire串行EEPROM的為2.5V(2K位,2.5伏,具上掉電數(shù)據(jù)保護(hù)電路,微型導(dǎo)線接口的EEPROM)
文件頁數(shù): 5/12頁
文件大小: 222K
代理商: 93LC56B
93LC56A/B
1997 Microchip Technology Inc.
Preliminary
DS21208A-page 5
3.4
ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
3.5
Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences at
the falling edge of the CS. Clocking of the CLK pin is not
necessary after the device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire ERAL cycle is com-
plete.
FIGURE 3-2:
ERASE TIMING
FIGURE 3-3:
ERAL TIMING
CS
CLK
DI
DO
T
CSL
CHECK STATUS
1
1
1
A
N
A
N
-1
A
N
-2
A0
T
SV
T
CZ
BUSY
READY
HIGH-Z
T
WC
HIGH-Z
CS
CLK
DI
DO
T
CSL
CHECK STATUS
1
0
0
1
0
X
X
T
SV
T
CZ
BUSY
READY
HIGH-Z
T
EC
HIGH-Z
Guaranteed at Vcc = 4.5V to +6.0V.
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參數(shù)描述
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93LC56B-/P 制造商:Microchip Technology 功能描述:2k(128~16) 2MHz 2.5V to 5.5V VA / Microwire 8DIP Bulk
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