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參數(shù)資料
| 型號： | 93LC46-I/MS |
| 元件分類： | PROM |
| 英文描述： | 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 510K |
| 代理商： | 93LC46-I/MS |
2002 Microchip Technology Inc.
DS21749A-page 7
93XX46, 93XX46A/B
2.5
ERASE ALL (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on ‘C’
devices where the rising edge of CLK before the last
data bit initiates the write cycle. Clocking of the CLK pin
is not necessary after the device has entered the ERAL
cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
CSL).
FIGURE 2-3:
ERAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
CS
CLK
DI
DO
T
CSL
CHECK STATUS
10
0
1
0
X
X
T
SV
T
CZ
BUSY
READY
HIGH-Z
T
EC
HIGH-Z
Ensured at Vcc = 4.5V to +5.5V.
CS
CLK
DI
DO
T
CSL
CHECK STATUS
10
0
1
0
X
X
T
SV
T
CZ
BUSY
READY
HIGH-Z
T
EC
HIGH-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 93C46T-I/MS | 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 93LC46T-E/MS | 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 93LC46-E/MS | 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 93LC46T-I/MS | 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 93C46-I/MS | 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 93LC46-IP | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46-ISL | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46-ISM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46-ISN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
| 93LC46-P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 2.0V Microwire Serial EEPROM |
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